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////////////////////////////////////////////////////////////////////////////
///@copyright Copyright (c) 2017, 传控科技 All rights reserved.
///-------------------------------------------------------------------------
/// @file msa300.c
/// @brief msa300 driver app
///-------------------------------------------------------------------------
/// @version 1.0
/// @author CC
/// @date 20170122
/// @note cc_AS_stc01
//////////////////////////////////////////////////////////////////////////////
#ifndef _MSA300_H
#define _MSA300_H
#include "bsp_config.h"
#include "msp_uart1.h"
#include "msp_iicMx.h"
#include "debug_drv.h"
/***********************************************************************
U51(SDO=1) int2 P33 ----------------U10(SDO=0) int2 P32----------------MCU----USB
0x4c 0x4e
AS1 AS2
**************************************************************************/
#define D_i2c_addr_AS1 0x4c // u51
//#define D_i2c_addr_AS2 0x4e
/* Register define for NSA asic */
#define MSA_REG_SPI_I2C 0x00
#define MSA_REG_WHO_AM_I 0x01
#define MSA_REG_ACC_X_LSB 0x02
#define MSA_REG_ACC_X_MSB 0x03
#define MSA_REG_ACC_Y_LSB 0x04
#define MSA_REG_ACC_Y_MSB 0x05
#define MSA_REG_ACC_Z_LSB 0x06
#define MSA_REG_ACC_Z_MSB 0x07
#define MSA_REG_Tape_Active_Status 0x0B
#define MSA_REG_G_RANGE 0x0f
#define MSA_REG_ODR_AXIS_DISABLE 0x10
#define MSA_REG_POWERMODE_BW 0x11
#define MSA_REG_SWAP_POLARITY 0x12
#define MSA_REG_FIFO_CTRL 0x14
#define MSA_REG_INTERRUPT_SETTINGS1 0x16
#define MSA_REG_INTERRUPT_SETTINGS2 0x17
#define MSA_REG_INTERRUPT_MAPPING1 0x19
#define MSA_REG_INTERRUPT_MAPPING2 0x1a
#define MSA_REG_INTERRUPT_MAPPING3 0x1b
#define MSA_REG_INT_PIN_CONFIG 0x20
#define MSA_REG_INT_LATCH 0x21
#define MSA_REG_ACTIVE_DURATION 0x27
#define MSA_REG_ACTIVE_THRESHOLD 0x28
#define MSA_REG_TAP_DURATION 0x2A
#define MSA_REG_TAP_THRESHOLD 0x2B
#define MSA_REG_CUSTOM_OFFSET_X 0x38
#define MSA_REG_CUSTOM_OFFSET_Y 0x39
#define MSA_REG_CUSTOM_OFFSET_Z 0x3a
#define MSA_REG_ENGINEERING_MODE 0x7f
#define MSA_REG_SENSITIVITY_TRIM_X 0x80
#define MSA_REG_SENSITIVITY_TRIM_Y 0x81
#define MSA_REG_SENSITIVITY_TRIM_Z 0x82
#define MSA_REG_COARSE_OFFSET_TRIM_X 0x83
#define MSA_REG_COARSE_OFFSET_TRIM_Y 0x84
#define MSA_REG_COARSE_OFFSET_TRIM_Z 0x85
#define MSA_REG_FINE_OFFSET_TRIM_X 0x86
#define MSA_REG_FINE_OFFSET_TRIM_Y 0x87
#define MSA_REG_FINE_OFFSET_TRIM_Z 0x88
#define MSA_REG_SENS_COMP 0x8c
#define MSA_REG_MEMS_OPTION 0x8f
#define MSA_REG_CHIP_INFO 0xc0
#define MSA_REG_CHIP_INFO_SECOND 0xc1
#define MSA_REG_SENS_COARSE_TRIM 0xd1
/*************
-------------------------------------------------------------------
Reg 0x0F(Resolution/Range)Read/Write
Bit7 Bit6 Bit5 Bit4 |Bit3 Bit2 |Bit1 Bit0 | Default
|RESOLUTION[1:0] | FS[1:0] | 0X00
RESOLUTION[1:0]: resolution of x/y/z axes,
00:14bit, 01:12bit, 10:10bit, 11:8bit
FS[1:0]: acceleration range of x/y/z axes,
00:+/-2g, 01:+/-4g, 10:+/-8g, 11:+/-16g
*********/
#define D_MSA_8BIT B0000_1100
#define D_MSA_12BIT B0000_0100
#define D_MSA_10BIT B0000_1000
#define D_MSA_14BIT B0000_0000
#define D_MSA_16G B0000_0011
#define D_MSA_8G B0000_0001
#define D_MSA_4G B0000_0010
#define D_MSA_2G B0000_0000
/**********
ODR Output data rate 1 1000 Hz
Reg0x10(ODR) Read/Write Default 0X0F
Bit7 Bit6 Bit5
X_AXIS_DIS Y_AXIS_DIS Z_AXIS_DIS
Bit4
Bit3 Bit2 Bit1 Bit0
ODR[3:0]
X_AXIS_DIS: 0:enable, 1:disable Y_AXIS_DIS: 0:enable, 1:disable Z_AXIS_DIS: 0:enable, 1:disable
ODR[3:0]:
0000:1Hz (not available in normal mode)
0001:1.95Hz (not available in normal mode)
0010:3.9Hz 0011:7.81Hz
0100:15.63Hz 0101: 31.25Hz 0110: 62.5Hz 0111: 125Hz 1000: 250Hz
1001: 500Hz (not available in low power mode)
1010-1111: (not available in low power mode)
Table 5: bandwidth under different ODR and BW settings in normal mode
ODR BW
1000Hz (1010-1111) 500Hz
500Hz (1001) 250Hz
250Hz (1000) 125Hz
125Hz (0111) 62.5Hz
62.5Hz (0110) 31.25Hz
31.25Hz (0101) 15.63Hz
15.63Hz (0100) 7.81Hz
7.81Hz (0011) 3.9Hz
3.9Hz (0010) 1.95Hz
MSA300 supports four different acceleration measurement ranges, it is selected
ODR BW
15.63Hz (0100) 7.81Hz
*********/
/// fixme: 实测和规格书不一致
#define D_AXIS_DIS_Y B1000_0000
#define D_AXIS_DIS_X B0100_0000
#define D_AXIS_DIS_Z B0010_0000
#define D_ODR_31Hz25 0x05
#define D_ODR_250Hz 0x08
#define D_ODR_125Hz 0x0f
#define D_ODR_15P63Hz B0000_0100
/**********
Reg0x11(Power Mode/Bandwidth) Read/Write
------------------------------------------------------------------
Bit7 Bit6 |Bit5 Bit4 Bit3 Bit2 Bit1 |Bit0 Default 0X9E
----------------------------------------------------------------------
PWR_MODE | LOW_POWER_BW[3:0] |
--------------------------------------------------------------------
PWR_MODE: 00:normal mode, 01:low power mode, 10/11 suspend mode
LOW_POWER_BW[3:0]:
0000-0010:1.95Hz
0011:3.9Hz,
0100:7.81Hz
0101:15.63Hz,
0110: 31.25Hz,
0111: 62.5Hz,
1000: 125Hz,
1001: 250Hz,
1010-1111:500Hz
***********/
//#define D_PowerMode_normal 0x00
//#define D_PowerMode_low 0x40
//#define D_PowerMode_suspend 0x80
#define D_lowPower_BW (0x0F<<1)
#define D_PowerMode_normal B0000_0000
#define D_PowerMode_suspend B1000_0000
#define D_PowerMode_lowpower B0100_0000
#define D_gs_LPBW1H9 (0<<1)
#define D_gs_LPBW3H9 (3<<1)
#define D_gs_LPBW7H8 (4<<1)
#define D_gs_LPBW15H (5<<1)
#define D_gs_LPBW31H (6<<1)
#define D_gs_LPBW62H (7<<1)
#define D_gs_LPBW125H (8<<1)
#define D_gs_LPBW250H (9<<1)
#define D_gs_LPBW500H (10<<1)
/**********
/**************************************
Reg 0x1B (Int_Map_2) Read/Write
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Default
Bit6 INT2_ORIENT
Bit5 INT2_S_TAP
Bit4 INT2_D_TAP
Bit2 INT2_ACTIVE
Bit1 RESERVED
Bit0 INT2_FREEFALL
0X00
INT2_ORIENT: map orientation interrupt to INT2, 0:disable, 1:enable INT2_S_TAP: map single tap interrupt to INT2, 0:disable, 1:enable INT2_D_TAP: map double tap interrupt to INT2, 0:disable, 1:enable INT2_ACTIVE: map active interrupt to INT2, 0:disable, 1:enable INT2_FREEFALL: map freefall interrupt to INT2, 0:disable, 1:enable
***************************************/
#define D_INT2_ORIENT BITN6
#define D_INT2_S_TAP BITN5
#define D_INT2_D_TAP BITN4
#define D_INT2_ACTIVE BITN2
#define D_INT2_FREEFALL BITN1
/**********************************************
Reg 0x20 (Int_Map_2) Read/Write
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Default 0X00
Bit3 INT2_OD
Bit2 NT2_LVL
Bit1 IINT1_OD
Bit0 INT1_LVL
INT2_OD: select output for INT2, 0: push-pull, 1:OD
INT2_LVL: select active level for INT2, 0: low, 1:high
INT1_OD: select output for INT1, 0: push-pull, 1:OD
INT1_LVL: select active level for INT1, 0: low, 1:high
***************************************/
#define D_INT2_pull 0
#define D_INT2_OD BITN3
#define D_INT2_LVL_high BITN2
#define D_INT2_LVL_low 0
#define D_INT1_pull 0
#define D_INT1_OD BITN1
#define D_INT1_LVL_high BITN0
#define D_INT1_LVL_low 0
/*************************************************************
U51(SDO=1) int2 P33 ----------------U10(SDO=0) int2 P32----------------MCU----USB
0x4c 0x4e
AS1 AS2
--------------------------------------------------------------------
Reg 0x16(Int_Set_0) Read/Write
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Default 0X00
-------------------------------------------------------------------
Tap
使 s_tap_en 使d_tap_en
: s_tap_int , d_tap_int
Bit6 ORIENT_INT_EN
Bit5 S_TAP_INT_EN
Bit4 D_TAP_INT_EN
Bit2 ACTIVE_INT_EN_Z
Bit1 ACTIVE_INT_EN_Y
Bit0 ACTIVE_INT_EN_X
-------------------------------------------------------------------
ORIENT_INT_EN: orient interrupt, 0:disable, 1:enable
S_TAP_INT_EN: single tap interrupt, 0:disable, 1:enable
D_TAP_INT_EN: double tap interrupt, 0:disable, 1:enable
ACTIVE_INT_EN_Z: active interrupt for the z axis, 0:disable, 1:enable
ACTIVE_INT_EN_Y: active interrupt for the y axis, 0:disable, 1:enable
ACTIVE_INT_EN_X: active interrupt for the x axis, 0:disable, 1:enable
reg 0x16Reg 0x19
-------------------------------------------------------------------
Reg 0x19(Int_Map_0) Read/Write
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Default
-------------------------------------------------------------------
INT1_ORIENT
INT1_S_TAP
INT1_D_TAP
INT1_ACTIVE
INT1_FREEFALL
0X00
-------------------------------------------------------------------
INT1_ORIENT: map orientation interrupt to INT1, 0:disable, 1:enable
INT1_S_TAP: map single tap interrupt to INT1, 0:disable, 1:enable
INT1_D_TAP: map double tap interrupt to INT1, 0:disable, 1:enable
INT1_ACTIVE: map active interrupt to INT1, 0:disable, 1:enable
INT1_FREEFALL: map freefall interrupt to INT1, 0:disable, 1:enable
-------------------------------------------------------------------
Reg 0x27 (Active_Dur) Read/Write
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Default
ACTIVE_DUR[1:0] 0X00
ACTIVE_DUR[1:0]: active duration time is (ACTIVE_DUR[1:0]+1)ms
-------------------------------------------------------------------
Reg 0x28(Active_Th) Read/Write
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Default
ACTIVE_TH[7:0] 0X14
ACTIVE_TH[7:0]: threshold of active interrupt
3.91mg/LSB(2g range)
7.81mg/LSB(4g range)
15.625mg/LSB(8g range)
31.25mg/LSB(16g range)
**************************************************************************/
#define ACTIVE_INT_EN_Z BITN2
#define ACTIVE_INT_EN_Y BITN1
#define ACTIVE_INT_EN_X BITN0
/***************************************
0x21 RESET_INT LATCH_INT[3:0] 0x00
latch_int Interrupt mode
0000 non-latched
0001 temporary latched 250ms
0010 temporary latched 500ms
0011 temporary latched 1s
0100 temporary latched 2s
0101 temporary latched 4s
0110 temporary latched 8s
0111 Latched
1000 non-latched
1001 temporary latched 1ms
1010 temporary latched 1ms
1011 temporary latched 2ms
1100 temporary latched 25ms
1101 temporary latched 50ms
1110 temporary latched 100ms
1111 Latched
_______/``latch period````\_______
****************************************/
#define D_no_latched 0x01
#define D_latch_250ms 0x01
#define D_latch_500ms 0x02
#define D_latch_1s 0x03
#define D_latch_2s 0x04
#define D_latch_4s 0x05
#define D_latch_8s 0x06
#define D_latched 0x07
#define D_no_latched2 0x08
#define D_latch_1ms 0x09
#define D_latch_1ms2 0x0a
#define D_latch_2ms 0x0B
#define D_latch_25ms 0x0C
#define D_latch_50ms 0x0D
#define D_latch_100ms 0x0E
#define D_latched2 0x0f
/****************************************************
Reg 0x09(Motion_Interrupt) :Read only
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Default 0X00
Bit6 ORIENT_INT
Bit5 S_TAP_INT
Bit4 D_TAP_INT
Bit2 ACTIVE_INT
Bit0 FREEFALL_INT
5s以上之后再工作 5
ORIENT_INT: orientation interrupt status,0:inactive,1:active
S_TAP_INT: single tap interrupt status,0:inactive,1:active
D_TAP_INT: double tap interrupt status,0:inactive,1:active
ACTIVE_INT: active interrupt status,0:inactive,1:active
FREEFALL_INT: freefall interrupt status,0:inactive,1:active
-------------------------------------------------------------------
Reg 0x0B(Tape_Active_Status) :Read only
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Default
TAP_SIGN
TAP_FIRST_X
TAP_FIRST_Y
TAP_FIRST_Z
ACTIVE_SIGN
ACTIVE_FIRST_X
ACTIVE_FIRST_Y
ACTIVE_FIRST_Z
0X00
-------------------------------------------------------------------
TAP_SIGN: sign of tap triggering signal, 0:positive,1:negative
TAP_FIRST_X: tap interrupt triggered by x axis, 1:positive,0:negative
TAP_FIRST_Y: tap interrupt triggered by y axis, 1:positive,0:negative
TAP_FIRST_Z: tap interrupt triggered by z axis, 1:positive,0:negative
ACTIVE_SIGN: sign of active interrupt, 0:positive,1:negative
ACTIVE_FIRST_X: active interrupt triggered by x axis, 1:positive,0:negative
ACTIVE_FIRST_Y: active interrupt triggered by y axis, 1:positive,0:negative
ACTIVE_FIRST_Z: active interrupt triggered by z axis, 1:positive,0:negative
***************************************************/
#define INT1_S_TAP_INT BITN5 ///单击中断
#define INT1_D_TAP_INT BITN4 ///双击中断
#define INT1_ACTIVE BITN2 /// 振动中断
#define D_Active_TH 0x28
#define D_Active_Dur 0x27
#define D_i2c_addr_AS1 0x4c // u51
#define D_i2c_addr_AS2 0x4e
#define D_i2c_addr_Gsensor 0x4c // u51
#define D_i2c_addr_AS1 0x4c // u51
#define D_i2c_addr_AS2 0x4e
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
// 最高400Khz 1/400 ms 2.5us
//Symbol Parameter Condition Min Max Unit
//fscl Clock frequency 400 kHz
#define D_as_ch_mun 1
struct _s_gsens_
{//8byte
U8 d[6];
U8 powermode;///
// U16 x;
// U16 y;
// U16 z;
};
extern struct _s_gsens_ s_as;
extern void L1_msa300_reg_init(void);
#define L1_ms300_reg_set(reg,dat) L2_IICMx_WriteCmd(D_iicch_MSA,D_i2c_addr_Gsensor,reg,dat)
////#define L1_ms300_reg_get(x,y) L2_I2C_ReadReg(D_i2c_addr_Gsensor,(x),1)
#define DL_ms300_int_open(); L1_ms300_reg_set(MSA_REG_INTERRUPT_MAPPING3,D_INT2_S_TAP|D_INT2_ACTIVE);
#define DL_ms300_int_close(); L1_ms300_reg_set(MSA_REG_INTERRUPT_MAPPING3,0);
#define L1_ms300_xyz_read(dat,num) L2_IICMx_ReadReg(D_iicch_MSA,D_i2c_addr_Gsensor,MSA_REG_ACC_X_LSB,dat,num)
/*********
extern void L1_as_readXYZ(unsigned char CH);
extern void L3_msa300_fun(U8 *pPara);
extern void L1_as_action(void);
extern void L1_as_WorkStatus(unsigned char d);
///L1_msa300_power(D_sleep);
extern void L1_msa300_power(U8 mode);
//读取reg地址的n个数据 sla.(reg) sla.(reg+1)................ sla.(reg+n)
void L2_IICMx_ReadReg(vtype ch,unsigned char sla,unsigned char reg,
unsigned char *r,unsigned char n)
#define L1_max30102_WB(reg,dat) L2_IICMx_WriteCmd(D_iicch_MSA,D_i2c_addr_Gsensor,reg,dat)
#define IIC_Read_Byte(adr,reg) L2_IICMx_Read1Reg1D(D_iicch_MSA,adr,reg)
#define L1_max30102_Read(adr,reg) L2_IICMx_Read1Reg1D(D_iicch_MSA,D_i2c_addr_Gsensor,reg)
#define L1_max30102_Read_Array(reg,dat,n) L2_IICMx_ReadReg(D_iicch_MSA,D_i2c_addr_Gsensor,reg,dat,n)
*******/
///#define D_PowerMode_low 0x5e
///#define D_PowerMode_low (0x50|D_gs_LPBW1H9)
//#define D_PowerMode_low 0x5e///(0x40|D_gs_LPBW62H)
#define LD_gsensor_power(Pmode) L2_IICMx_WriteCmd(D_iicch_MSA,D_i2c_addr_Gsensor,MSA_REG_POWERMODE_BW,Pmode);s_as.powermode=Pmode
#endif // #ifndef _MSA300_H