26 changed files with 3152 additions and 756 deletions
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{ |
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"files.associations": { |
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"UART0.C": "cpp" |
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} |
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} |
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////////////////////////////////////////////////////////////////////////////
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///@copyright Copyright (c) 2018, 传控科技 All rights reserved.
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///-------------------------------------------------------------------------
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/// @file msp_eeprom.c
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/// @brief msp @ driver config
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///-------------------------------------------------------------------------
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/// @version 1.0
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/// @author CC
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/// @date 20190106
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/// @note cc_AS_stc02 由stc-isp v6.0860
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//////////////////////////////////////////////////////////////////////////////
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#include "chipid.h" |
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#include "../bsp/bsp_config.h" |
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#define MSP_ID_LEN 7 |
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void L0_id_get(U8 *id) |
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{ |
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U8 i = 0; |
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char *ID = (char idata *)0xf1; |
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for(i=0;i<MSP_ID_LEN;i++) |
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{ |
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id[i] = ID[i]; |
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} |
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} |
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void L0_id_get_rom(U8 *id) |
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{ |
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U8 i = 0; |
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char *ID = (char code *)(D_MCU_SPEC_PARAM_CHIPID); |
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for(i=0;i<MSP_ID_LEN;i++) |
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{ |
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id[i] = ID[i]; |
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} |
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} |
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#if 1 |
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void L0_id_main(void) |
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{ |
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U8 i,id[MSP_ID_LEN]; |
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L0_id_get_rom(id); |
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for(i=0;i<MSP_ID_LEN;i++) |
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{ |
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L0_uart0_uchex(id[i]); |
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} |
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while(1); |
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} |
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#endif |
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#ifndef __STC15F2K60S2_H_ |
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#define __STC15F2K60S2_H_ |
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// stc_stc15w.h
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#include<intrins.h> |
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/////////////////////////////////////////////////
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//注意: STC15W4K32S4系列的芯片,上电后所有与PWM相关的IO口均为
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// 高阻态,需将这些口设置为准双向口或强推挽模式方可正常使用
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//相关IO: P0.6/P0.7/P1.6/P1.7/P2.1/P2.2
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// P2.3/P2.7/P3.7/P4.2/P4.4/P4.5
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/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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//包含本头文件后,不用另外再包含"REG51.H"
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//内核特殊功能寄存器 // 复位值 描述
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sfr ACC = 0xE0; //0000,0000 累加器Accumulator
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sfr B = 0xF0; //0000,0000 B寄存器
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sfr PSW = 0xD0; //0000,0000 程序状态字
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sbit CY = PSW^7; |
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sbit AC = PSW^6; |
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sbit F0 = PSW^5; |
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sbit RS1 = PSW^4; |
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sbit RS0 = PSW^3; |
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sbit OV = PSW^2; |
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sbit P = PSW^0; |
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sfr SP = 0x81; //0000,0111 堆栈指针
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sfr DPL = 0x82; //0000,0000 数据指针低字节
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sfr DPH = 0x83; //0000,0000 数据指针高字节
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//I/O 口特殊功能寄存器
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sfr P0 = 0x80; //1111,1111 端口0
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sbit P00 = P0^0; |
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sbit P01 = P0^1; |
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sbit P02 = P0^2; |
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sbit P03 = P0^3; |
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sbit P04 = P0^4; |
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sbit P05 = P0^5; |
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sbit P06 = P0^6; |
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sbit P07 = P0^7; |
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sfr P1 = 0x90; //1111,1111 端口1
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sbit P10 = P1^0; |
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sbit P11 = P1^1; |
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sbit P12 = P1^2; |
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sbit P13 = P1^3; |
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sbit P14 = P1^4; |
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sbit P15 = P1^5; |
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sbit P16 = P1^6; |
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sbit P17 = P1^7; |
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sfr P2 = 0xA0; //1111,1111 端口2
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sbit P20 = P2^0; |
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sbit P21 = P2^1; |
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sbit P22 = P2^2; |
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sbit P23 = P2^3; |
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sbit P24 = P2^4; |
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sbit P25 = P2^5; |
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sbit P26 = P2^6; |
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sbit P27 = P2^7; |
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sfr P3 = 0xB0; //1111,1111 端口3
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sbit P30 = P3^0; |
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sbit P31 = P3^1; |
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sbit P32 = P3^2; |
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sbit P33 = P3^3; |
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sbit P34 = P3^4; |
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sbit P35 = P3^5; |
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sbit P36 = P3^6; |
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sbit P37 = P3^7; |
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sfr P4 = 0xC0; //1111,1111 端口4
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sbit P40 = P4^0; |
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sbit P41 = P4^1; |
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sbit P42 = P4^2; |
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sbit P43 = P4^3; |
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sbit P44 = P4^4; |
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sbit P45 = P4^5; |
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sbit P46 = P4^6; |
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sbit P47 = P4^7; |
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sfr P5 = 0xC8; //xxxx,1111 端口5
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sbit P50 = P5^0; |
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sbit P51 = P5^1; |
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sbit P52 = P5^2; |
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sbit P53 = P5^3; |
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sbit P54 = P5^4; |
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sbit P55 = P5^5; |
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sbit P56 = P5^6; |
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sbit P57 = P5^7; |
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sfr P6 = 0xE8; //0000,0000 端口6
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sbit P60 = P6^0; |
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sbit P61 = P6^1; |
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sbit P62 = P6^2; |
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sbit P63 = P6^3; |
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sbit P64 = P6^4; |
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sbit P65 = P6^5; |
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sbit P66 = P6^6; |
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sbit P67 = P6^7; |
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sfr P7 = 0xF8; //0000,0000 端口7
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sbit P70 = P7^0; |
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sbit P71 = P7^1; |
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sbit P72 = P7^2; |
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sbit P73 = P7^3; |
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sbit P74 = P7^4; |
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sbit P75 = P7^5; |
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sbit P76 = P7^6; |
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sbit P77 = P7^7; |
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sfr P0M0 = 0x94; //0000,0000 端口0模式寄存器0
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sfr P0M1 = 0x93; //0000,0000 端口0模式寄存器1
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sfr P1M0 = 0x92; //0000,0000 端口1模式寄存器0
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sfr P1M1 = 0x91; //0000,0000 端口1模式寄存器1
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sfr P2M0 = 0x96; //0000,0000 端口2模式寄存器0
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sfr P2M1 = 0x95; //0000,0000 端口2模式寄存器1
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sfr P3M0 = 0xB2; //0000,0000 端口3模式寄存器0
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sfr P3M1 = 0xB1; //0000,0000 端口3模式寄存器1
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sfr P4M0 = 0xB4; //0000,0000 端口4模式寄存器0
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sfr P4M1 = 0xB3; //0000,0000 端口4模式寄存器1
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sfr P5M0 = 0xCA; //0000,0000 端口5模式寄存器0
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sfr P5M1 = 0xC9; //0000,0000 端口5模式寄存器1
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sfr P6M0 = 0xCC; //0000,0000 端口6模式寄存器0
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sfr P6M1 = 0xCB; //0000,0000 端口6模式寄存器1
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sfr P7M0 = 0xE2; //0000,0000 端口7模式寄存器0
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sfr P7M1 = 0xE1; //0000,0000 端口7模式寄存器1
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//系统管理特殊功能寄存器
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sfr PCON = 0x87; //0001,0000 电源控制寄存器
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sfr AUXR = 0x8E; //0000,0000 辅助寄存器
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#define TOx12 BITN7 |
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#define T1x12 BITN6 |
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#define UART_M0x6 BITN5 //串口1模式0速度 =0 12倍 = 1 两倍
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#define T2R BITN4 //定时器2 运行 =1
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#define T2_C BITN3 //定时器/计数器选择
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#define T2x12 BITN2 |
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#define EXTRAM BITN1 |
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#define S1ST2 BITN0 //串口1选择定时器1 =0 选择定时器2 =1
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sfr AUXR1 = 0xA2; //0000,0000 辅助寄存器1
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sfr P_SW1 = 0xA2; //0000,0000 外设端口切换寄存器1
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sfr CLK_DIV = 0x97; //0000,0000 时钟分频控制寄存器
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sfr BUS_SPEED = 0xA1; //xx10,x011 总线速度控制寄存器
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sfr P1ASF = 0x9D; //0000,0000 端口1模拟功能配置寄存器
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sfr P_SW2 = 0xBA; //0xxx,x000 外设端口切换寄存器
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//中断特殊功能寄存器
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sfr IE = 0xA8; //0000,0000 中断控制寄存器
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sbit EA = IE^7; |
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sbit ELVD = IE^6; |
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sbit EADC = IE^5; |
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sbit ES = IE^4; |
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sbit ET1 = IE^3; |
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sbit EX1 = IE^2; |
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sbit ET0 = IE^1; |
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sbit EX0 = IE^0; |
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sfr IP = 0xB8; //0000,0000 中断优先级寄存器
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sbit PPCA = IP^7; |
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sbit PLVD = IP^6; |
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sbit PADC = IP^5; |
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sbit PS = IP^4; |
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sbit PT1 = IP^3; |
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sbit PX1 = IP^2; |
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sbit PT0 = IP^1; |
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sbit PX0 = IP^0; |
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sfr IE2 = 0xAF; //0000,0000 中断控制寄存器2
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/// 不可位寻址
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#define ET4 BITN6 |
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#define ET3 BITN5 |
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#define ES4 BITN4 |
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#define ES3 BITN3 |
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#define ET2 BITN2 |
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#define ESPI BITN1 |
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#define ES2 BITN0 |
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sfr IP2 = 0xB5; //xxxx,xx00 中断优先级寄存器2
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sfr INT_CLKO = 0x8F; //0000,0000 外部中断与时钟输出控制寄存器
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//定时器特殊功能寄存器
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sfr TCON = 0x88; //0000,0000 T0/T1控制寄存器
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sbit TF1 = TCON^7; |
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sbit TR1 = TCON^6; |
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sbit TF0 = TCON^5; |
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sbit TR0 = TCON^4; |
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sbit IE1 = TCON^3; |
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sbit IT1 = TCON^2; |
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sbit IE0 = TCON^1; |
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sbit IT0 = TCON^0; |
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sfr TMOD = 0x89; //0000,0000 T0/T1模式寄存器
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sfr TL0 = 0x8A; //0000,0000 T0低字节
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sfr TL1 = 0x8B; //0000,0000 T1低字节
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sfr TH0 = 0x8C; //0000,0000 T0高字节
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sfr TH1 = 0x8D; //0000,0000 T1高字节
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sfr T4T3M = 0xD1; //0000,0000 T3/T4模式寄存器
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sfr T3T4M = 0xD1; //0000,0000 T3/T4模式寄存器
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sfr T4H = 0xD2; //0000,0000 T4高字节
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sfr T4L = 0xD3; //0000,0000 T4低字节
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sfr T3H = 0xD4; //0000,0000 T3高字节
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sfr T3L = 0xD5; //0000,0000 T3低字节
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sfr T2H = 0xD6; //0000,0000 T2高字节
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sfr T2L = 0xD7; //0000,0000 T2低字节
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sfr WKTCL = 0xAA; //0000,0000 掉电唤醒定时器低字节
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sfr WKTCH = 0xAB; //0000,0000 掉电唤醒定时器高字节
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sfr WDT_CONTR = 0xC1; //0000,0000 看门狗控制寄存器
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//串行口特殊功能寄存器
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sfr SCON = 0x98; //0000,0000 串口1控制寄存器
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sbit SM0 = SCON^7; |
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sbit SM1 = SCON^6; |
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sbit SM2 = SCON^5; |
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sbit REN = SCON^4; |
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sbit TB8 = SCON^3; |
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sbit RB8 = SCON^2; |
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sbit TI = SCON^1; |
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sbit RI = SCON^0; |
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//sfr SBUF = 0x99; //xxxx,xxxx 串口1数据寄存器
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//sfr S2CON = 0x9A; //0000,0000 串口2控制寄存器
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//sfr S2BUF = 0x9B; //xxxx,xxxx 串口2数据寄存器
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//sfr SADDR = 0xA9; //0000,0000 从机地址寄存器
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//sfr SADEN = 0xB9; //0000,0000 从机地址屏蔽寄存器
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sfr SBUF = 0x99; //Serial Data Buffer
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sfr SBUF0 = 0x99; //Serial Data Buffer xxxx,xxxx
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sfr SADEN = 0xB9; //Slave Address Mask 0000,0000
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sfr SADDR = 0xA9; //Slave Address 0000,0000
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//-----------------------------------
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// 7 6 5 4 3 2 1 0 Reset Value
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sfr S2CON = 0x9A; //S2 Control S2SM0 S2SM1 S2SM2 S2REN S2TB8 S2RB8 S2TI S2RI 00000000B
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#define S2SM0 BITN7 |
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#define S2ST4 BITN6 |
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#define S2SM2 BITN5 |
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#define S2REN BITN4 |
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#define S2TB8 BITN3 |
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#define S2RB8 BITN2 |
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#define S2TI BITN1 |
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#define S2RI BITN0 |
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sfr S2BUF = 0x9B; //S2 Serial Buffer xxxx,xxxx
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//sfr BRT = 0x9C; //S2 Baud-Rate Timer 0000,0000
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//---------------------------------------------------------------
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sfr S3CON = 0xAC; //0000,0000 串口3控制寄存器
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#define S3SM0 BITN7 |
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#define S3ST4 BITN6 |
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#define S3SM2 BITN5 |
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#define S3REN BITN4 |
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#define S3TB8 BITN3 |
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#define S3RB8 BITN2 |
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#define S3TI BITN1 |
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#define S3RI BITN0 |
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sfr S3BUF = 0xAD; //xxxx,xxxx 串口3数据寄存器
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//---------------------------------------------------------------
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sfr S4CON = 0x84; //0000,0000 串口4控制寄存器
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#define S4SM0 BITN7 |
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#define S4ST4 BITN6 |
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#define S4SM2 BITN5 |
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#define S4REN BITN4 |
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#define S4TB8 BITN3 |
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#define S4RB8 BITN2 |
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#define S4TI BITN1 |
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#define S4RI BITN0 |
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sfr S4BUF = 0x85; //xxxx,xxxx 串口4数据寄存器
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//ADC 特殊功能寄存器
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sfr ADC_CONTR = 0xBC; //0000,0000 A/D转换控制寄存器
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sfr ADC_RES = 0xBD; //0000,0000 A/D转换结果高8位
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sfr ADC_RESL = 0xBE; //0000,0000 A/D转换结果低2位
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//SPI 特殊功能寄存器
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sfr SPSTAT = 0xCD; //00xx,xxxx SPI状态寄存器
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sfr SPCTL = 0xCE; //0000,0100 SPI控制寄存器
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sfr SPDAT = 0xCF; //0000,0000 SPI数据寄存器
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//IAP/ISP 特殊功能寄存器
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sfr IAP_DATA = 0xC2; //0000,0000 EEPROM数据寄存器
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sfr IAP_ADDRH = 0xC3; //0000,0000 EEPROM地址高字节
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sfr IAP_ADDRL = 0xC4; //0000,0000 EEPROM地址第字节
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sfr IAP_CMD = 0xC5; //xxxx,xx00 EEPROM命令寄存器
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sfr IAP_TRIG = 0xC6; //0000,0000 EEPRPM命令触发寄存器
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sfr IAP_CONTR = 0xC7; //0000,x000 EEPROM控制寄存器
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//PCA/PWM 特殊功能寄存器
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sfr CCON = 0xD8; //00xx,xx00 PCA控制寄存器
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sbit CF = CCON^7; |
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sbit CR = CCON^6; |
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sbit CCF2 = CCON^2; |
||||
|
sbit CCF1 = CCON^1; |
||||
|
sbit CCF0 = CCON^0; |
||||
|
sfr CMOD = 0xD9; //0xxx,x000 PCA 工作模式寄存器
|
||||
|
sfr CL = 0xE9; //0000,0000 PCA计数器低字节
|
||||
|
sfr CH = 0xF9; //0000,0000 PCA计数器高字节
|
||||
|
sfr CCAPM0 = 0xDA; //0000,0000 PCA模块0的PWM寄存器
|
||||
|
sfr CCAPM1 = 0xDB; //0000,0000 PCA模块1的PWM寄存器
|
||||
|
sfr CCAPM2 = 0xDC; //0000,0000 PCA模块2的PWM 寄存器
|
||||
|
sfr CCAP0L = 0xEA; //0000,0000 PCA模块0的捕捉/比较寄存器低字节
|
||||
|
sfr CCAP1L = 0xEB; //0000,0000 PCA模块1的捕捉/比较寄存器低字节
|
||||
|
sfr CCAP2L = 0xEC; //0000,0000 PCA模块2的捕捉/比较寄存器低字节
|
||||
|
sfr PCA_PWM0 = 0xF2; //xxxx,xx00 PCA模块0的PWM寄存器
|
||||
|
sfr PCA_PWM1 = 0xF3; //xxxx,xx00 PCA模块1的PWM寄存器
|
||||
|
sfr PCA_PWM2 = 0xF4; //xxxx,xx00 PCA模块1的PWM寄存器
|
||||
|
sfr CCAP0H = 0xFA; //0000,0000 PCA模块0的捕捉/比较寄存器高字节
|
||||
|
sfr CCAP1H = 0xFB; //0000,0000 PCA模块1的捕捉/比较寄存器高字节
|
||||
|
sfr CCAP2H = 0xFC; //0000,0000 PCA模块2的捕捉/比较寄存器高字节
|
||||
|
|
||||
|
//比较器特殊功能寄存器
|
||||
|
sfr CMPCR1 = 0xE6; //0000,0000 比较器控制寄存器1
|
||||
|
sfr CMPCR2 = 0xE7; //0000,0000 比较器控制寄存器2
|
||||
|
|
||||
|
//增强型PWM波形发生器特殊功能寄存器
|
||||
|
sfr PWMCFG = 0xf1; //x000,0000 PWM配置寄存器
|
||||
|
sfr PWMCR = 0xf5; //0000,0000 PWM控制寄存器
|
||||
|
sfr PWMIF = 0xf6; //x000,0000 PWM中断标志寄存器
|
||||
|
sfr PWMFDCR = 0xf7; //xx00,0000 PWM外部异常检测控制寄存器
|
||||
|
|
||||
|
//如下特殊功能寄存器位于扩展RAM区域
|
||||
|
//访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写
|
||||
|
#define PWMC (*(unsigned int volatile xdata *)0xfff0) |
||||
|
#define PWMCH (*(unsigned char volatile xdata *)0xfff0) |
||||
|
#define PWMCL (*(unsigned char volatile xdata *)0xfff1) |
||||
|
#define PWMCKS (*(unsigned char volatile xdata *)0xfff2) |
||||
|
#define PWM2T1 (*(unsigned int volatile xdata *)0xff00) |
||||
|
#define PWM2T1H (*(unsigned char volatile xdata *)0xff00) |
||||
|
#define PWM2T1L (*(unsigned char volatile xdata *)0xff01) |
||||
|
#define PWM2T2 (*(unsigned int volatile xdata *)0xff02) |
||||
|
#define PWM2T2H (*(unsigned char volatile xdata *)0xff02) |
||||
|
#define PWM2T2L (*(unsigned char volatile xdata *)0xff03) |
||||
|
#define PWM2CR (*(unsigned char volatile xdata *)0xff04) |
||||
|
#define PWM3T1 (*(unsigned int volatile xdata *)0xff10) |
||||
|
#define PWM3T1H (*(unsigned char volatile xdata *)0xff10) |
||||
|
#define PWM3T1L (*(unsigned char volatile xdata *)0xff11) |
||||
|
#define PWM3T2 (*(unsigned int volatile xdata *)0xff12) |
||||
|
#define PWM3T2H (*(unsigned char volatile xdata *)0xff12) |
||||
|
#define PWM3T2L (*(unsigned char volatile xdata *)0xff13) |
||||
|
#define PWM3CR (*(unsigned char volatile xdata *)0xff14) |
||||
|
#define PWM4T1 (*(unsigned int volatile xdata *)0xff20) |
||||
|
#define PWM4T1H (*(unsigned char volatile xdata *)0xff20) |
||||
|
#define PWM4T1L (*(unsigned char volatile xdata *)0xff21) |
||||
|
#define PWM4T2 (*(unsigned int volatile xdata *)0xff22) |
||||
|
#define PWM4T2H (*(unsigned char volatile xdata *)0xff22) |
||||
|
#define PWM4T2L (*(unsigned char volatile xdata *)0xff23) |
||||
|
#define PWM4CR (*(unsigned char volatile xdata *)0xff24) |
||||
|
#define PWM5T1 (*(unsigned int volatile xdata *)0xff30) |
||||
|
#define PWM5T1H (*(unsigned char volatile xdata *)0xff30) |
||||
|
#define PWM5T1L (*(unsigned char volatile xdata *)0xff31) |
||||
|
#define PWM5T2 (*(unsigned int volatile xdata *)0xff32) |
||||
|
#define PWM5T2H (*(unsigned char volatile xdata *)0xff32) |
||||
|
#define PWM5T2L (*(unsigned char volatile xdata *)0xff33) |
||||
|
#define PWM5CR (*(unsigned char volatile xdata *)0xff34) |
||||
|
#define PWM6T1 (*(unsigned int volatile xdata *)0xff40) |
||||
|
#define PWM6T1H (*(unsigned char volatile xdata *)0xff40) |
||||
|
#define PWM6T1L (*(unsigned char volatile xdata *)0xff41) |
||||
|
#define PWM6T2 (*(unsigned int volatile xdata *)0xff42) |
||||
|
#define PWM6T2H (*(unsigned char volatile xdata *)0xff42) |
||||
|
#define PWM6T2L (*(unsigned char volatile xdata *)0xff43) |
||||
|
#define PWM6CR (*(unsigned char volatile xdata *)0xff44) |
||||
|
#define PWM7T1 (*(unsigned int volatile xdata *)0xff50) |
||||
|
#define PWM7T1H (*(unsigned char volatile xdata *)0xff50) |
||||
|
#define PWM7T1L (*(unsigned char volatile xdata *)0xff51) |
||||
|
#define PWM7T2 (*(unsigned int volatile xdata *)0xff52) |
||||
|
#define PWM7T2H (*(unsigned char volatile xdata *)0xff52) |
||||
|
#define PWM7T2L (*(unsigned char volatile xdata *)0xff53) |
||||
|
#define PWM7CR (*(unsigned char volatile xdata *)0xff54) |
||||
|
|
||||
|
/////////////////////////////////////////////////
|
||||
|
|
||||
|
|
||||
|
|
||||
|
/* P3 */ |
||||
|
sbit RD = 0xB7; |
||||
|
sbit WR = 0xB6; |
||||
|
sbit T1 = 0xB5; |
||||
|
sbit T0 = 0xB4; |
||||
|
sbit INT1 = 0xB3; |
||||
|
sbit INT0 = 0xB2; |
||||
|
sbit TXD = 0xB1; |
||||
|
sbit RXD = 0xB0; |
||||
|
|
||||
|
|
||||
|
|
||||
|
|
||||
|
|
||||
|
/// >>>>> add by cc
|
||||
|
|
||||
|
|
||||
|
//sbit P34=P3^4; //定义SDA数据线
|
||||
|
//sbit P35=P3^5; //定义SCL时钟线
|
||||
|
#define mBIT_1(X,N) X|= (1<<N) |
||||
|
#define mBIT_0(X,N) X&=~(1<<N) |
||||
|
#define mBIT_G(X,N) (X&(1<<N)) |
||||
|
|
||||
|
//高阻状态
|
||||
|
#define P0_conf_in(n) mBIT_1(P0M1,n);mBIT_0(P0M0,n); |
||||
|
#define P1_conf_in(n) mBIT_1(P1M1,n);mBIT_0(P1M0,n); |
||||
|
#define P2_conf_in(n) mBIT_1(P2M1,n);mBIT_0(P2M0,n); |
||||
|
#define P2_conf_port(n) mBIT_0(P2M1,n);mBIT_0(P2M0,n); |
||||
|
|
||||
|
|
||||
|
#define P3_conf_in(n) mBIT_1(P3M1,n);mBIT_0(P3M0,n); |
||||
|
|
||||
|
#define P3_conf_port(n) mBIT_0(P3M1,n);mBIT_0(P3M0,n); |
||||
|
|
||||
|
|
||||
|
#define P4_conf_in(n) mBIT_1(P4M1,n);mBIT_0(P4M0,n); |
||||
|
#define P5_conf_in(n) mBIT_1(P5M1,n);mBIT_0(P5M0,n); |
||||
|
#define NOP() _nop_() |
||||
|
|
||||
|
|
||||
|
#define D_stdIO_P0_ALL() P0M1=0;P0M0=0; |
||||
|
#define D_HighI_P0_ALL() P0M1=0;P0M0=0XFF; |
||||
|
#define D_HighR_P0_ALL() P0M1=0XFF;P0M0=0; |
||||
|
#define D_OpenD_P0_ALL() P0M1=0XFF;P0M0=0XFF; |
||||
|
|
||||
|
#define D_stdIO_P1_ALL() P1M1=0;P1M0=0; |
||||
|
#define D_HighI_P1_ALL() P1M1=0;P1M0=0XFF; |
||||
|
#define D_HighR_P1_ALL() P1M1=0XFF;P1M0=0; |
||||
|
#define D_OpenD_P1_ALL() P1M1=0XFF;P1M0=0XFF; |
||||
|
|
||||
|
//// n: BITN0---BITN7
|
||||
|
#define D_stdIO_P0(BITN) BITN_0(P0M1,BITN);BITN_0(P0M0,BITN); //////00 准双向口 灌电流20mA 拉电流270-150uS
|
||||
|
#define D_HighI_P0(BITN) BITN_0(P0M1,BITN);BITN_1(P0M0,BITN); //////01 推挽输出 20mA 加限流
|
||||
|
#define D_HighR_P0(BITN) BITN_1(P0M1,BITN);BITN_0(P0M0,BITN); /////////10 高阻
|
||||
|
#define D_OpenD_P0(BITN) BITN_1(P0M1,BITN);BITN_1(P0M0,BITN); /////11 开漏 open-Drain 内部上拉电阻断开 开漏模式既可以度外部状态也可以对外输出高低电平
|
||||
|
|
||||
|
#define D_stdIO_P1(BITN) BITN_0(P1M1,BITN);BITN_0(P1M0,BITN); //////00 准双向口 灌电流20mA 拉电流270-150uS
|
||||
|
#define D_HighI_P1(BITN) BITN_0(P1M1,BITN);BITN_1(P1M0,BITN); //////01 推挽输出 20mA 加限流
|
||||
|
#define D_HighR_P1(BITN) BITN_1(P1M1,BITN);BITN_0(P1M0,BITN); /////////10 高阻
|
||||
|
#define D_OpenD_P1(BITN) BITN_1(P1M1,BITN);BITN_1(P1M0,BITN); /////11 开漏 open-Drain 内部上拉电阻断开 开漏模式既可以度外部状态也可以对外输出高低电平
|
||||
|
|
||||
|
#define D_stdIO_P2(BITN) BITN_0(P2M1,BITN);BITN_0(P2M0,BITN); //////00 准双向口 灌电流20mA 拉电流270-150uS
|
||||
|
#define D_HighI_P2(BITN) BITN_0(P2M1,BITN);BITN_1(P2M0,BITN); //////01 推挽输出 20mA 加限流
|
||||
|
#define D_HighR_P2(BITN) BITN_1(P2M1,BITN);BITN_0(P2M0,BITN); /////////10 高阻
|
||||
|
#define D_OpenD_P2(BITN) BITN_1(P2M1,BITN);BITN_1(P2M0,BITN); /////11 开漏 open-Drain 内部上拉电阻断开 开漏模式既可以度外部状态也可以对外输出高低电平
|
||||
|
|
||||
|
#define D_stdIO_P3(BITN) BITN_0(P3M1,BITN);BITN_0(P3M0,BITN); //////00 准双向口 灌电流20mA 拉电流270-150uS
|
||||
|
#define D_HighI_P3(BITN) BITN_0(P3M1,BITN);BITN_1(P3M0,BITN); //////01 推挽输出 20mA 加限流
|
||||
|
#define D_HighR_P3(BITN) BITN_1(P3M1,BITN);BITN_0(P3M0,BITN); /////////10 高阻
|
||||
|
#define D_OpenD_P3(BITN) BITN_1(P3M1,BITN);BITN_1(P3M0,BITN); /////11 开漏 open-Drain 内部上拉电阻断开 开漏模式既可以度外部状态也可以对外输出高低电平
|
||||
|
|
||||
|
#define D_stdIO_P4(BITN) BITN_0(P4M1,BITN);BITN_0(P4M0,BITN); //////00 准双向口 灌电流20mA 拉电流270-150uS
|
||||
|
#define D_HighI_P4(BITN) BITN_0(P4M1,BITN);BITN_1(P4M0,BITN); //////01 推挽输出 20mA 加限流
|
||||
|
#define D_HighR_P4(BITN) BITN_1(P4M1,BITN);BITN_0(P4M0,BITN); /////////10 高阻
|
||||
|
#define D_OpenD_P4(BITN) BITN_1(P4M1,BITN);BITN_1(P4M0,BITN); /////11 开漏 open-Drain 内部上拉电阻断开 开漏模式既可以度外部状态也可以对外输出高低电平
|
||||
|
|
||||
|
#define D_stdIO_P5(BITN) BITN_0(P5M1,BITN);BITN_0(P5M0,BITN); //////00 准双向口 灌电流20mA 拉电流270-150uS
|
||||
|
#define D_HighI_P5(BITN) BITN_0(P5M1,BITN);BITN_1(P5M0,BITN); //////01 推挽输出 20mA 加限流
|
||||
|
#define D_HighR_P5(BITN) BITN_1(P5M1,BITN);BITN_0(P5M0,BITN); /////////10 高阻
|
||||
|
#define D_OpenD_P5(BITN) BITN_1(P5M1,BITN);BITN_1(P5M0,BITN); /////11 开漏 open-Drain 内部上拉电阻断开 开漏模式既可以度外部状态也可以对外输出高低电平
|
||||
|
|
||||
|
#define D_stdIO_P6(BITN) BITN_0(P6M1,BITN);BITN_0(P6M0,BITN); //////00 准双向口 灌电流20mA 拉电流270-150uS
|
||||
|
#define D_HighI_P6(BITN) BITN_0(P6M1,BITN);BITN_1(P6M0,BITN); //////01 推挽输出 20mA 加限流
|
||||
|
#define D_HighR_P6(BITN) BITN_1(P6M1,BITN);BITN_0(P6M0,BITN); /////////10 高阻
|
||||
|
#define D_OpenD_P6(BITN) BITN_1(P6M1,BITN);BITN_1(P6M0,BITN); /////11 开漏 open-Drain 内部上拉电阻断开 开漏模式既可以度外部状态也可以对外输出高低电平
|
||||
|
|
||||
|
#define D_stdIO_P7(BITN) BITN_0(P7M1,BITN);BITN_0(P7M0,BITN); //////00 准双向口 灌电流20mA 拉电流270-150uS
|
||||
|
#define D_HighI_P7(BITN) BITN_0(P7M1,BITN);BITN_1(P7M0,BITN); //////01 推挽输出 20mA 加限流
|
||||
|
#define D_HighR_P7(BITN) BITN_1(P7M1,BITN);BITN_0(P7M0,BITN); /////////10 高阻
|
||||
|
#define D_OpenD_P7(BITN) BITN_1(P7M1,BITN);BITN_1(P7M0,BITN); /////11 开漏 open-Drain 内部上拉电阻断开 开漏模式既可以度外部状态也可以对外输出高低电平
|
||||
|
|
||||
|
|
||||
|
#endif |
||||
|
|
||||
|
|
||||
|
|
||||
|
|
||||
|
|
||||
|
|
@ -0,0 +1,593 @@ |
|||||
|
#ifndef __STC8F_H_ |
||||
|
#define __STC8F_H_ |
||||
|
|
||||
|
/////////////////////////////////////////////////
|
||||
|
|
||||
|
//包含本头文件后,不用另外再包含"REG51.H"
|
||||
|
|
||||
|
//内核特殊功能寄存器
|
||||
|
sfr ACC = 0xe0; |
||||
|
sfr B = 0xf0; |
||||
|
sfr PSW = 0xd0; |
||||
|
sbit CY = PSW^7; |
||||
|
sbit AC = PSW^6; |
||||
|
sbit F0 = PSW^5; |
||||
|
sbit RS1 = PSW^4; |
||||
|
sbit RS0 = PSW^3; |
||||
|
sbit OV = PSW^2; |
||||
|
sbit F1 = PSW^1; |
||||
|
sbit P = PSW^0; |
||||
|
sfr SP = 0x81; |
||||
|
sfr DPL = 0x82; |
||||
|
sfr DPH = 0x83; |
||||
|
sfr TA = 0xae; |
||||
|
sfr DPS = 0xe3; |
||||
|
sfr DPL1 = 0xe4; |
||||
|
sfr DPH1 = 0xe5; |
||||
|
|
||||
|
|
||||
|
//I/O 口特殊功能寄存器
|
||||
|
sfr P0 = 0x80; |
||||
|
sfr P1 = 0x90; |
||||
|
sfr P2 = 0xa0; |
||||
|
sfr P3 = 0xb0; |
||||
|
sfr P4 = 0xc0; |
||||
|
sfr P5 = 0xc8; |
||||
|
sfr P6 = 0xe8; |
||||
|
sfr P7 = 0xf8; |
||||
|
sfr P0M0 = 0x94; |
||||
|
sfr P0M1 = 0x93; |
||||
|
sfr P1M0 = 0x92; |
||||
|
sfr P1M1 = 0x91; |
||||
|
sfr P2M0 = 0x96; |
||||
|
sfr P2M1 = 0x95; |
||||
|
sfr P3M0 = 0xb2; |
||||
|
sfr P3M1 = 0xb1; |
||||
|
sfr P4M0 = 0xb4; |
||||
|
sfr P4M1 = 0xb3; |
||||
|
sfr P5M0 = 0xca; |
||||
|
sfr P5M1 = 0xc9; |
||||
|
sfr P6M0 = 0xcc; |
||||
|
sfr P6M1 = 0xcb; |
||||
|
sfr P7M0 = 0xe2; |
||||
|
sfr P7M1 = 0xe1; |
||||
|
|
||||
|
sbit P00 = P0^0; |
||||
|
sbit P01 = P0^1; |
||||
|
sbit P02 = P0^2; |
||||
|
sbit P03 = P0^3; |
||||
|
sbit P04 = P0^4; |
||||
|
sbit P05 = P0^5; |
||||
|
sbit P06 = P0^6; |
||||
|
sbit P07 = P0^7; |
||||
|
sbit P10 = P1^0; |
||||
|
sbit P11 = P1^1; |
||||
|
sbit P12 = P1^2; |
||||
|
sbit P13 = P1^3; |
||||
|
sbit P14 = P1^4; |
||||
|
sbit P15 = P1^5; |
||||
|
sbit P16 = P1^6; |
||||
|
sbit P17 = P1^7; |
||||
|
sbit P20 = P2^0; |
||||
|
sbit P21 = P2^1; |
||||
|
sbit P22 = P2^2; |
||||
|
sbit P23 = P2^3; |
||||
|
sbit P24 = P2^4; |
||||
|
sbit P25 = P2^5; |
||||
|
sbit P26 = P2^6; |
||||
|
sbit P27 = P2^7; |
||||
|
sbit P30 = P3^0; |
||||
|
sbit P31 = P3^1; |
||||
|
sbit P32 = P3^2; |
||||
|
sbit P33 = P3^3; |
||||
|
sbit P34 = P3^4; |
||||
|
sbit P35 = P3^5; |
||||
|
sbit P36 = P3^6; |
||||
|
sbit P37 = P3^7; |
||||
|
sbit P40 = P4^0; |
||||
|
sbit P41 = P4^1; |
||||
|
sbit P42 = P4^2; |
||||
|
sbit P43 = P4^3; |
||||
|
sbit P44 = P4^4; |
||||
|
sbit P45 = P4^5; |
||||
|
sbit P46 = P4^6; |
||||
|
sbit P47 = P4^7; |
||||
|
sbit P50 = P5^0; |
||||
|
sbit P51 = P5^1; |
||||
|
sbit P52 = P5^2; |
||||
|
sbit P53 = P5^3; |
||||
|
sbit P54 = P5^4; |
||||
|
sbit P55 = P5^5; |
||||
|
sbit P56 = P5^6; |
||||
|
sbit P57 = P5^7; |
||||
|
sbit P60 = P6^0; |
||||
|
sbit P61 = P6^1; |
||||
|
sbit P62 = P6^2; |
||||
|
sbit P63 = P6^3; |
||||
|
sbit P64 = P6^4; |
||||
|
sbit P65 = P6^5; |
||||
|
sbit P66 = P6^6; |
||||
|
sbit P67 = P6^7; |
||||
|
sbit P70 = P7^0; |
||||
|
sbit P71 = P7^1; |
||||
|
sbit P72 = P7^2; |
||||
|
sbit P73 = P7^3; |
||||
|
sbit P74 = P7^4; |
||||
|
sbit P75 = P7^5; |
||||
|
sbit P76 = P7^6; |
||||
|
sbit P77 = P7^7; |
||||
|
|
||||
|
//如下特殊功能寄存器位于扩展RAM区域
|
||||
|
//访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写
|
||||
|
#define P0PU (*(unsigned char volatile xdata *)0xfe10) |
||||
|
#define P1PU (*(unsigned char volatile xdata *)0xfe11) |
||||
|
#define P2PU (*(unsigned char volatile xdata *)0xfe12) |
||||
|
#define P3PU (*(unsigned char volatile xdata *)0xfe13) |
||||
|
#define P4PU (*(unsigned char volatile xdata *)0xfe14) |
||||
|
#define P5PU (*(unsigned char volatile xdata *)0xfe15) |
||||
|
#define P6PU (*(unsigned char volatile xdata *)0xfe16) |
||||
|
#define P7PU (*(unsigned char volatile xdata *)0xfe17) |
||||
|
#define P0NCS (*(unsigned char volatile xdata *)0xfe18) |
||||
|
#define P1NCS (*(unsigned char volatile xdata *)0xfe19) |
||||
|
#define P2NCS (*(unsigned char volatile xdata *)0xfe1a) |
||||
|
#define P3NCS (*(unsigned char volatile xdata *)0xfe1b) |
||||
|
#define P4NCS (*(unsigned char volatile xdata *)0xfe1c) |
||||
|
#define P5NCS (*(unsigned char volatile xdata *)0xfe1d) |
||||
|
#define P6NCS (*(unsigned char volatile xdata *)0xfe1e) |
||||
|
#define P7NCS (*(unsigned char volatile xdata *)0xfe1f) |
||||
|
|
||||
|
//系统管理特殊功能寄存器
|
||||
|
sfr PCON = 0x87; |
||||
|
#define SMOD 0x80 |
||||
|
#define SMOD0 0x40 |
||||
|
#define LVDF 0x20 |
||||
|
#define POF 0x10 |
||||
|
#define GF1 0x08 |
||||
|
#define GF0 0x04 |
||||
|
#define PD 0x02 |
||||
|
#define IDL 0x01 |
||||
|
sfr AUXR = 0x8e; |
||||
|
#define T0x12 0x80 |
||||
|
#define T1x12 0x40 |
||||
|
#define UART_M0x6 0x20 |
||||
|
#define T2R 0x10 |
||||
|
#define T2_CT 0x08 |
||||
|
#define T2x12 0x04 |
||||
|
#define EXTRAM 0x02 |
||||
|
#define S1ST2 0x01 |
||||
|
sfr AUXR2 = 0x97; |
||||
|
#define TXLNRX 0x10 |
||||
|
sfr BUS_SPEED = 0xa1; |
||||
|
sfr P_SW1 = 0xa2; |
||||
|
sfr P_SW2 = 0xba; |
||||
|
#define EAXFR 0x80 |
||||
|
sfr VOCTRL = 0xbb; |
||||
|
sfr RSTCFG = 0xff; |
||||
|
|
||||
|
//如下特殊功能寄存器位于扩展RAM区域
|
||||
|
//访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写
|
||||
|
#define CKSEL (*(unsigned char volatile xdata *)0xfe00) |
||||
|
#define CLKDIV (*(unsigned char volatile xdata *)0xfe01) |
||||
|
#define IRC24MCR (*(unsigned char volatile xdata *)0xfe02) |
||||
|
#define XOSCCR (*(unsigned char volatile xdata *)0xfe03) |
||||
|
#define IRC32KCR (*(unsigned char volatile xdata *)0xfe04) |
||||
|
|
||||
|
//中断特殊功能寄存器
|
||||
|
sfr IE = 0xa8; |
||||
|
sbit EA = IE^7; |
||||
|
sbit ELVD = IE^6; |
||||
|
sbit EADC = IE^5; |
||||
|
sbit ES = IE^4; |
||||
|
sbit ET1 = IE^3; |
||||
|
sbit EX1 = IE^2; |
||||
|
sbit ET0 = IE^1; |
||||
|
sbit EX0 = IE^0; |
||||
|
sfr IE2 = 0xaf; |
||||
|
#define ET4 0x40 |
||||
|
#define ET3 0x20 |
||||
|
#define ES4 0x10 |
||||
|
#define ES3 0x08 |
||||
|
#define ET2 0x04 |
||||
|
#define ESPI 0x02 |
||||
|
#define ES2 0x01 |
||||
|
|
||||
|
sfr IP = 0xb8; |
||||
|
sbit PPCA = IP^7; |
||||
|
sbit PLVD = IP^6; |
||||
|
sbit PADC = IP^5; |
||||
|
sbit PS = IP^4; |
||||
|
sbit PT1 = IP^3; |
||||
|
sbit PX1 = IP^2; |
||||
|
sbit PT0 = IP^1; |
||||
|
sbit PX0 = IP^0; |
||||
|
sfr IP2 = 0xb5; |
||||
|
#define PI2C 0x40 |
||||
|
#define PCMP 0x20 |
||||
|
#define PX4 0x10 |
||||
|
#define PPWMFD 0x08 |
||||
|
#define PPWM 0x04 |
||||
|
#define PSPI 0x02 |
||||
|
#define PS2 0x01 |
||||
|
sfr IPH = 0xb7; |
||||
|
#define PPCAH 0x80 |
||||
|
#define PLVDH 0x40 |
||||
|
#define PADCH 0x20 |
||||
|
#define PSH 0x10 |
||||
|
#define PT1H 0x08 |
||||
|
#define PX1H 0x04 |
||||
|
#define PT0H 0x02 |
||||
|
#define PX0H 0x01 |
||||
|
sfr IP2H = 0xb6; |
||||
|
#define PI2CH 0x40 |
||||
|
#define PCMPH 0x20 |
||||
|
#define PX4H 0x10 |
||||
|
#define PPWMFDH 0x08 |
||||
|
#define PPWMH 0x04 |
||||
|
#define PSPIH 0x02 |
||||
|
#define PS2H 0x01 |
||||
|
sfr INTCLKO = 0x8f; |
||||
|
#define EX4 0x40 |
||||
|
#define EX3 0x20 |
||||
|
#define EX2 0x10 |
||||
|
#define T2CLKO 0x04 |
||||
|
#define T1CLKO 0x02 |
||||
|
#define T0CLKO 0x01 |
||||
|
sfr AUXINTIF = 0xef; |
||||
|
#define INT4IF 0x40 |
||||
|
#define INT3IF 0x20 |
||||
|
#define INT2IF 0x10 |
||||
|
#define T4IF 0x04 |
||||
|
#define T3IF 0x02 |
||||
|
#define T2IF 0x01 |
||||
|
|
||||
|
//定时器特殊功能寄存器
|
||||
|
sfr TCON = 0x88; |
||||
|
sbit TF1 = TCON^7; |
||||
|
sbit TR1 = TCON^6; |
||||
|
sbit TF0 = TCON^5; |
||||
|
sbit TR0 = TCON^4; |
||||
|
sbit IE1 = TCON^3; |
||||
|
sbit IT1 = TCON^2; |
||||
|
sbit IE0 = TCON^1; |
||||
|
sbit IT0 = TCON^0; |
||||
|
sfr TMOD = 0x89; |
||||
|
#define T1_GATE 0x80 |
||||
|
#define T1_CT 0x40 |
||||
|
#define T1_M1 0x20 |
||||
|
#define T1_M0 0x10 |
||||
|
#define T0_GATE 0x08 |
||||
|
#define T0_CT 0x04 |
||||
|
#define T0_M1 0x02 |
||||
|
#define T0_M0 0x01 |
||||
|
sfr TL0 = 0x8a; |
||||
|
sfr TL1 = 0x8b; |
||||
|
sfr TH0 = 0x8c; |
||||
|
sfr TH1 = 0x8d; |
||||
|
sfr T4T3M = 0xd1; |
||||
|
#define T4R 0x80 |
||||
|
#define T4_CT 0x40 |
||||
|
#define T4x12 0x20 |
||||
|
#define T4CLKO 0x10 |
||||
|
#define T3R 0x08 |
||||
|
#define T3_CT 0x04 |
||||
|
#define T3x12 0x02 |
||||
|
#define T3CLKO 0x01 |
||||
|
sfr T4H = 0xd2; |
||||
|
sfr T4L = 0xd3; |
||||
|
sfr T3H = 0xd4; |
||||
|
sfr T3L = 0xd5; |
||||
|
sfr T2H = 0xd6; |
||||
|
sfr T2L = 0xd7; |
||||
|
sfr TH4 = 0xd2; |
||||
|
sfr TL4 = 0xd3; |
||||
|
sfr TH3 = 0xd4; |
||||
|
sfr TL3 = 0xd5; |
||||
|
sfr TH2 = 0xd6; |
||||
|
sfr TL2 = 0xd7; |
||||
|
sfr WKTCL = 0xaa; |
||||
|
sfr WKTCH = 0xab; |
||||
|
#define WKTEN 0x80 |
||||
|
sfr WDT_CONTR = 0xc1; |
||||
|
#define WDT_FLAG 0x80 |
||||
|
#define EN_WDT 0x20 |
||||
|
#define CLR_WDT 0x10 |
||||
|
#define IDL_WDT 0x08 |
||||
|
|
||||
|
//串行口特殊功能寄存器
|
||||
|
sfr SCON = 0x98; |
||||
|
sbit SM0 = SCON^7; |
||||
|
sbit SM1 = SCON^6; |
||||
|
sbit SM2 = SCON^5; |
||||
|
sbit REN = SCON^4; |
||||
|
sbit TB8 = SCON^3; |
||||
|
sbit RB8 = SCON^2; |
||||
|
sbit TI = SCON^1; |
||||
|
sbit RI = SCON^0; |
||||
|
sfr SBUF = 0x99; |
||||
|
sfr S2CON = 0x9a; |
||||
|
#define S2SM0 0x80 |
||||
|
#define S2ST4 0x40 |
||||
|
#define S2SM2 0x20 |
||||
|
#define S2REN 0x10 |
||||
|
#define S2TB8 0x08 |
||||
|
#define S2RB8 0x04 |
||||
|
#define S2TI 0x02 |
||||
|
#define S2RI 0x01 |
||||
|
sfr S2BUF = 0x9b; |
||||
|
sfr S3CON = 0xac; |
||||
|
#define S3SM0 0x80 |
||||
|
#define S3ST4 0x40 |
||||
|
#define S3SM2 0x20 |
||||
|
#define S3REN 0x10 |
||||
|
#define S3TB8 0x08 |
||||
|
#define S3RB8 0x04 |
||||
|
#define S3TI 0x02 |
||||
|
#define S3RI 0x01 |
||||
|
sfr S3BUF = 0xad; |
||||
|
sfr S4CON = 0x84; |
||||
|
#define S4SM0 0x80 |
||||
|
#define S4ST4 0x40 |
||||
|
#define S4SM2 0x20 |
||||
|
#define S4REN 0x10 |
||||
|
#define S4TB8 0x08 |
||||
|
#define S4RB8 0x04 |
||||
|
#define S4TI 0x02 |
||||
|
#define S4RI 0x01 |
||||
|
sfr S4BUF = 0x85; |
||||
|
sfr SADDR = 0xa9; |
||||
|
sfr SADEN = 0xb9; |
||||
|
|
||||
|
//ADC 特殊功能寄存器
|
||||
|
sfr ADC_CONTR = 0xbc; |
||||
|
#define ADC_POWER 0x80 |
||||
|
#define ADC_START 0x40 |
||||
|
#define ADC_FLAG 0x20 |
||||
|
sfr ADC_RES = 0xbd; |
||||
|
sfr ADC_RESL = 0xbe; |
||||
|
sfr ADCCFG = 0xde; |
||||
|
#define ADC_RESFMT 0x20 |
||||
|
|
||||
|
//SPI 特殊功能寄存器
|
||||
|
sfr SPSTAT = 0xcd; |
||||
|
#define SPIF 0x80 |
||||
|
#define WCOL 0x40 |
||||
|
sfr SPCTL = 0xce; |
||||
|
#define SSIG 0x80 |
||||
|
#define SPEN 0x40 |
||||
|
#define DORD 0x20 |
||||
|
#define MSTR 0x10 |
||||
|
#define CPOL 0x08 |
||||
|
#define CPHA 0x04 |
||||
|
sfr SPDAT = 0xcf; |
||||
|
|
||||
|
//IAP/ISP 特殊功能寄存器
|
||||
|
sfr IAP_DATA = 0xc2; |
||||
|
sfr IAP_ADDRH = 0xc3; |
||||
|
sfr IAP_ADDRL = 0xc4; |
||||
|
sfr IAP_CMD = 0xc5; |
||||
|
#define IAP_IDL 0x00 |
||||
|
#define IAP_READ 0x01 |
||||
|
#define IAP_WRITE 0x02 |
||||
|
#define IAP_ERASE 0x03 |
||||
|
sfr IAP_TRIG = 0xc6; |
||||
|
sfr IAP_CONTR = 0xc7; |
||||
|
#define IAPEN 0x80 |
||||
|
#define SWBS 0x40 |
||||
|
#define SWRST 0x20 |
||||
|
#define CMD_FAIL 0x10 |
||||
|
sfr ISP_DATA = 0xc2; |
||||
|
sfr ISP_ADDRH = 0xc3; |
||||
|
sfr ISP_ADDRL = 0xc4; |
||||
|
sfr ISP_CMD = 0xc5; |
||||
|
sfr ISP_TRIG = 0xc6; |
||||
|
sfr ISP_CONTR = 0xc7; |
||||
|
|
||||
|
//比较器特殊功能寄存器
|
||||
|
sfr CMPCR1 = 0xe6; |
||||
|
#define CMPEN 0x80 |
||||
|
#define CMPIF 0x40 |
||||
|
#define PIE 0x20 |
||||
|
#define NIE 0x10 |
||||
|
#define PIS 0x08 |
||||
|
#define NIS 0x04 |
||||
|
#define CMPOE 0x02 |
||||
|
#define CMPRES 0x01 |
||||
|
sfr CMPCR2 = 0xe7; |
||||
|
#define INVCMPO 0x80 |
||||
|
#define DISFLT 0x40 |
||||
|
|
||||
|
//PCA/PWM 特殊功能寄存器
|
||||
|
sfr CCON = 0xd8; |
||||
|
sbit CF = CCON^7; |
||||
|
sbit CR = CCON^6; |
||||
|
sbit CCF3 = CCON^3; |
||||
|
sbit CCF2 = CCON^2; |
||||
|
sbit CCF1 = CCON^1; |
||||
|
sbit CCF0 = CCON^0; |
||||
|
sfr CMOD = 0xd9; |
||||
|
#define CIDL 0x80 |
||||
|
#define ECF 0x01 |
||||
|
sfr CL = 0xe9; |
||||
|
sfr CH = 0xf9; |
||||
|
sfr CCAPM0 = 0xda; |
||||
|
#define ECOM0 0x40 |
||||
|
#define CCAPP0 0x20 |
||||
|
#define CCAPN0 0x10 |
||||
|
#define MAT0 0x08 |
||||
|
#define TOG0 0x04 |
||||
|
#define PWM0 0x02 |
||||
|
#define ECCF0 0x01 |
||||
|
sfr CCAPM1 = 0xdb; |
||||
|
#define ECOM1 0x40 |
||||
|
#define CCAPP1 0x20 |
||||
|
#define CCAPN1 0x10 |
||||
|
#define MAT1 0x08 |
||||
|
#define TOG1 0x04 |
||||
|
#define PWM1 0x02 |
||||
|
#define ECCF1 0x01 |
||||
|
sfr CCAPM2 = 0xdc; |
||||
|
#define ECOM2 0x40 |
||||
|
#define CCAPP2 0x20 |
||||
|
#define CCAPN2 0x10 |
||||
|
#define MAT2 0x08 |
||||
|
#define TOG2 0x04 |
||||
|
#define PWM2 0x02 |
||||
|
#define ECCF2 0x01 |
||||
|
sfr CCAPM3 = 0xdd; |
||||
|
#define ECOM3 0x40 |
||||
|
#define CCAPP3 0x20 |
||||
|
#define CCAPN3 0x10 |
||||
|
#define MAT3 0x08 |
||||
|
#define TOG3 0x04 |
||||
|
#define PWM3 0x02 |
||||
|
#define ECCF3 0x01 |
||||
|
sfr CCAP0L = 0xea; |
||||
|
sfr CCAP1L = 0xeb; |
||||
|
sfr CCAP2L = 0xec; |
||||
|
sfr CCAP3L = 0xed; |
||||
|
sfr CCAP0H = 0xfa; |
||||
|
sfr CCAP1H = 0xfb; |
||||
|
sfr CCAP2H = 0xfc; |
||||
|
sfr CCAP3H = 0xfd; |
||||
|
sfr PCA_PWM0 = 0xf2; |
||||
|
sfr PCA_PWM1 = 0xf3; |
||||
|
sfr PCA_PWM2 = 0xf4; |
||||
|
sfr PCA_PWM3 = 0xf5; |
||||
|
|
||||
|
//增强型PWM波形发生器特殊功能寄存器
|
||||
|
sfr PWMCFG = 0xf1; |
||||
|
#define CBIF 0x80 |
||||
|
#define ETADC 0x40 |
||||
|
sfr PWMIF = 0xf6; |
||||
|
#define C7IF 0x80 |
||||
|
#define C6IF 0x40 |
||||
|
#define C5IF 0x20 |
||||
|
#define C4IF 0x10 |
||||
|
#define C3IF 0x08 |
||||
|
#define C2IF 0x04 |
||||
|
#define C1IF 0x02 |
||||
|
#define C0IF 0x01 |
||||
|
sfr PWMFDCR = 0xf7; |
||||
|
#define INVCMP 0x80 |
||||
|
#define INVIO 0x40 |
||||
|
#define ENFD 0x20 |
||||
|
#define FLTFLIO 0x10 |
||||
|
#define EFDI 0x08 |
||||
|
#define FDCMP 0x04 |
||||
|
#define FDIO 0x02 |
||||
|
#define FDIF 0x01 |
||||
|
sfr PWMCR = 0xfe; |
||||
|
#define ENPWM 0x80 |
||||
|
#define ECBI 0x40 |
||||
|
|
||||
|
//如下特殊功能寄存器位于扩展RAM区域
|
||||
|
//访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写
|
||||
|
#define PWMC (*(unsigned int volatile xdata *)0xfff0) |
||||
|
#define PWMCH (*(unsigned char volatile xdata *)0xfff0) |
||||
|
#define PWMCL (*(unsigned char volatile xdata *)0xfff1) |
||||
|
#define PWMCKS (*(unsigned char volatile xdata *)0xfff2) |
||||
|
#define TADCP (*(unsigned char volatile xdata *)0xfff3) |
||||
|
#define TADCPH (*(unsigned char volatile xdata *)0xfff3) |
||||
|
#define TADCPL (*(unsigned char volatile xdata *)0xfff4) |
||||
|
#define PWM0T1 (*(unsigned int volatile xdata *)0xff00) |
||||
|
#define PWM0T1H (*(unsigned char volatile xdata *)0xff00) |
||||
|
#define PWM0T1L (*(unsigned char volatile xdata *)0xff01) |
||||
|
#define PWM0T2 (*(unsigned int volatile xdata *)0xff02) |
||||
|
#define PWM0T2H (*(unsigned char volatile xdata *)0xff02) |
||||
|
#define PWM0T2L (*(unsigned char volatile xdata *)0xff03) |
||||
|
#define PWM0CR (*(unsigned char volatile xdata *)0xff04) |
||||
|
#define PWM0HLD (*(unsigned char volatile xdata *)0xff05) |
||||
|
#define PWM1T1 (*(unsigned int volatile xdata *)0xff10) |
||||
|
#define PWM1T1H (*(unsigned char volatile xdata *)0xff10) |
||||
|
#define PWM1T1L (*(unsigned char volatile xdata *)0xff11) |
||||
|
#define PWM1T2 (*(unsigned int volatile xdata *)0xff12) |
||||
|
#define PWM1T2H (*(unsigned char volatile xdata *)0xff12) |
||||
|
#define PWM1T2L (*(unsigned char volatile xdata *)0xff13) |
||||
|
#define PWM1CR (*(unsigned char volatile xdata *)0xff14) |
||||
|
#define PWM1HLD (*(unsigned char volatile xdata *)0xff15) |
||||
|
#define PWM2T1 (*(unsigned int volatile xdata *)0xff20) |
||||
|
#define PWM2T1H (*(unsigned char volatile xdata *)0xff20) |
||||
|
#define PWM2T1L (*(unsigned char volatile xdata *)0xff21) |
||||
|
#define PWM2T2 (*(unsigned int volatile xdata *)0xff22) |
||||
|
#define PWM2T2H (*(unsigned char volatile xdata *)0xff22) |
||||
|
#define PWM2T2L (*(unsigned char volatile xdata *)0xff23) |
||||
|
#define PWM2CR (*(unsigned char volatile xdata *)0xff24) |
||||
|
#define PWM2HLD (*(unsigned char volatile xdata *)0xff25) |
||||
|
#define PWM3T1 (*(unsigned int volatile xdata *)0xff30) |
||||
|
#define PWM3T1H (*(unsigned char volatile xdata *)0xff30) |
||||
|
#define PWM3T1L (*(unsigned char volatile xdata *)0xff31) |
||||
|
#define PWM3T2 (*(unsigned int volatile xdata *)0xff32) |
||||
|
#define PWM3T2H (*(unsigned char volatile xdata *)0xff32) |
||||
|
#define PWM3T2L (*(unsigned char volatile xdata *)0xff33) |
||||
|
#define PWM3CR (*(unsigned char volatile xdata *)0xff34) |
||||
|
#define PWM3HLD (*(unsigned char volatile xdata *)0xff35) |
||||
|
#define PWM4T1 (*(unsigned int volatile xdata *)0xff40) |
||||
|
#define PWM4T1H (*(unsigned char volatile xdata *)0xff40) |
||||
|
#define PWM4T1L (*(unsigned char volatile xdata *)0xff41) |
||||
|
#define PWM4T2 (*(unsigned int volatile xdata *)0xff42) |
||||
|
#define PWM4T2H (*(unsigned char volatile xdata *)0xff42) |
||||
|
#define PWM4T2L (*(unsigned char volatile xdata *)0xff43) |
||||
|
#define PWM4CR (*(unsigned char volatile xdata *)0xff44) |
||||
|
#define PWM4HLD (*(unsigned char volatile xdata *)0xff45) |
||||
|
#define PWM5T1 (*(unsigned int volatile xdata *)0xff50) |
||||
|
#define PWM5T1H (*(unsigned char volatile xdata *)0xff50) |
||||
|
#define PWM5T1L (*(unsigned char volatile xdata *)0xff51) |
||||
|
#define PWM5T2 (*(unsigned int volatile xdata *)0xff52) |
||||
|
#define PWM5T2H (*(unsigned char volatile xdata *)0xff52) |
||||
|
#define PWM5T2L (*(unsigned char volatile xdata *)0xff53) |
||||
|
#define PWM5CR (*(unsigned char volatile xdata *)0xff54) |
||||
|
#define PWM5HLD (*(unsigned char volatile xdata *)0xff55) |
||||
|
#define PWM6T1 (*(unsigned int volatile xdata *)0xff60) |
||||
|
#define PWM6T1H (*(unsigned char volatile xdata *)0xff60) |
||||
|
#define PWM6T1L (*(unsigned char volatile xdata *)0xff61) |
||||
|
#define PWM6T2 (*(unsigned int volatile xdata *)0xff62) |
||||
|
#define PWM6T2H (*(unsigned char volatile xdata *)0xff62) |
||||
|
#define PWM6T2L (*(unsigned char volatile xdata *)0xff63) |
||||
|
#define PWM6CR (*(unsigned char volatile xdata *)0xff64) |
||||
|
#define PWM6HLD (*(unsigned char volatile xdata *)0xff65) |
||||
|
#define PWM7T1 (*(unsigned int volatile xdata *)0xff70) |
||||
|
#define PWM7T1H (*(unsigned char volatile xdata *)0xff70) |
||||
|
#define PWM7T1L (*(unsigned char volatile xdata *)0xff71) |
||||
|
#define PWM7T2 (*(unsigned int volatile xdata *)0xff72) |
||||
|
#define PWM7T2H (*(unsigned char volatile xdata *)0xff72) |
||||
|
#define PWM7T2L (*(unsigned char volatile xdata *)0xff73) |
||||
|
#define PWM7CR (*(unsigned char volatile xdata *)0xff74) |
||||
|
#define PWM7HLD (*(unsigned char volatile xdata *)0xff75) |
||||
|
|
||||
|
//I2C特殊功能寄存器
|
||||
|
//如下特殊功能寄存器位于扩展RAM区域
|
||||
|
//访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写
|
||||
|
#define I2CCFG (*(unsigned char volatile xdata *)0xfe80) |
||||
|
#define ENI2C 0x80 |
||||
|
#define MSSL 0x40 |
||||
|
#define I2CMSCR (*(unsigned char volatile xdata *)0xfe81) |
||||
|
#define EMSI 0x80 |
||||
|
#define I2CMSST (*(unsigned char volatile xdata *)0xfe82) |
||||
|
#define MSBUSY 0x80 |
||||
|
#define MSIF 0x40 |
||||
|
#define MSACKI 0x02 |
||||
|
#define MSACKO 0x01 |
||||
|
#define I2CSLCR (*(unsigned char volatile xdata *)0xfe83) |
||||
|
#define ESTAI 0x40 |
||||
|
#define ERXI 0x20 |
||||
|
#define ETXI 0x10 |
||||
|
#define ESTOI 0x08 |
||||
|
#define SLRST 0x01 |
||||
|
#define I2CSLST (*(unsigned char volatile xdata *)0xfe84) |
||||
|
#define SLBUSY 0x80 |
||||
|
#define STAIF 0x40 |
||||
|
#define RXIF 0x20 |
||||
|
#define TXIF 0x10 |
||||
|
#define STOIF 0x08 |
||||
|
#define TXING 0x04 |
||||
|
#define SLACKI 0x02 |
||||
|
#define SLACKO 0x01 |
||||
|
#define I2CSLADR (*(unsigned char volatile xdata *)0xfe85) |
||||
|
#define I2CTXD (*(unsigned char volatile xdata *)0xfe86) |
||||
|
#define I2CRXD (*(unsigned char volatile xdata *)0xfe87) |
||||
|
|
||||
|
/////////////////////////////////////////////////
|
||||
|
|
||||
|
#endif |
||||
|
|
||||
|
|
@ -0,0 +1,746 @@ |
|||||
|
#ifndef __STC8G_H_ |
||||
|
#define __STC8G_H_ |
||||
|
|
||||
|
// STC_stc8a8k.h
|
||||
|
#include<intrins.h> |
||||
|
/////////////////////////////////////////////////
|
||||
|
//注意: STC15W4K32S4系列的芯片,上电后所有与PWM相关的IO口均为
|
||||
|
// 高阻态,需将这些口设置为准双向口或强推挽模式方可正常使用
|
||||
|
//相关IO: P0.6/P0.7/P1.6/P1.7/P2.1/P2.2
|
||||
|
// P2.3/P2.7/P3.7/P4.2/P4.4/P4.5
|
||||
|
/////////////////////////////////////////////////
|
||||
|
|
||||
|
/////////////////////////////////////////////////
|
||||
|
|
||||
|
//包含本头文件后,不用另外再包含"REG51.H"
|
||||
|
|
||||
|
|
||||
|
/////////////////////////////////////////////////
|
||||
|
|
||||
|
//包含本头文件后,不用另外再包含"REG51.H"
|
||||
|
|
||||
|
sfr P0 = 0x80; |
||||
|
sbit P00 = P0^0; |
||||
|
sbit P01 = P0^1; |
||||
|
sbit P02 = P0^2; |
||||
|
sbit P03 = P0^3; |
||||
|
sbit P04 = P0^4; |
||||
|
sbit P05 = P0^5; |
||||
|
sbit P06 = P0^6; |
||||
|
sbit P07 = P0^7; |
||||
|
sfr SP = 0x81; |
||||
|
sfr DPL = 0x82; |
||||
|
sfr DPH = 0x83; |
||||
|
sfr S4CON = 0x84; |
||||
|
sfr S4BUF = 0x85; |
||||
|
sfr PCON = 0x87; |
||||
|
sfr TCON = 0x88; |
||||
|
sbit TF1 = TCON^7; |
||||
|
sbit TR1 = TCON^6; |
||||
|
sbit TF0 = TCON^5; |
||||
|
sbit TR0 = TCON^4; |
||||
|
sbit IE1 = TCON^3; |
||||
|
sbit IT1 = TCON^2; |
||||
|
sbit IE0 = TCON^1; |
||||
|
sbit IT0 = TCON^0; |
||||
|
sfr TMOD = 0x89; |
||||
|
sfr TL0 = 0x8A; |
||||
|
sfr TL1 = 0x8B; |
||||
|
sfr TH0 = 0x8C; |
||||
|
sfr TH1 = 0x8D; |
||||
|
sfr AUXR = 0x8E; |
||||
|
sfr INTCLKO = 0x8F; |
||||
|
sfr P1 = 0x90; |
||||
|
sbit P10 = P1^0; |
||||
|
sbit P11 = P1^1; |
||||
|
sbit P12 = P1^2; |
||||
|
sbit P13 = P1^3; |
||||
|
sbit P14 = P1^4; |
||||
|
sbit P15 = P1^5; |
||||
|
sbit P16 = P1^6; |
||||
|
sbit P17 = P1^7; |
||||
|
sfr P1M1 = 0x91; |
||||
|
sfr P1M0 = 0x92; |
||||
|
sfr P0M1 = 0x93; |
||||
|
sfr P0M0 = 0x94; |
||||
|
sfr P2M1 = 0x95; |
||||
|
sfr P2M0 = 0x96; |
||||
|
sfr SCON = 0x98; |
||||
|
sbit SM0 = SCON^7; |
||||
|
sbit SM1 = SCON^6; |
||||
|
sbit SM2 = SCON^5; |
||||
|
sbit REN = SCON^4; |
||||
|
sbit TB8 = SCON^3; |
||||
|
sbit RB8 = SCON^2; |
||||
|
sbit TI = SCON^1; |
||||
|
sbit RI = SCON^0; |
||||
|
sfr SBUF = 0x99; |
||||
|
sfr S2CON = 0x9A; |
||||
|
sfr S2BUF = 0x9B; |
||||
|
sfr IRCBAND = 0x9D; |
||||
|
sfr LIRTRIM = 0x9E; |
||||
|
sfr IRTRIM = 0x9F; |
||||
|
sfr P2 = 0xA0; |
||||
|
sbit P20 = P2^0; |
||||
|
sbit P21 = P2^1; |
||||
|
sbit P22 = P2^2; |
||||
|
sbit P23 = P2^3; |
||||
|
sbit P24 = P2^4; |
||||
|
sbit P25 = P2^5; |
||||
|
sbit P26 = P2^6; |
||||
|
sbit P27 = P2^7; |
||||
|
sfr P_SW1 = 0xA2; |
||||
|
sfr IE = 0xA8; |
||||
|
sbit EA = IE^7; |
||||
|
sbit ELVD = IE^6; |
||||
|
sbit EADC = IE^5; |
||||
|
sbit ES = IE^4; |
||||
|
sbit ET1 = IE^3; |
||||
|
sbit EX1 = IE^2; |
||||
|
sbit ET0 = IE^1; |
||||
|
sbit EX0 = IE^0; |
||||
|
sfr SADDR = 0xA9; |
||||
|
sfr WKTCL = 0xAA; |
||||
|
sfr WKTCH = 0xAB; |
||||
|
sfr S3CON = 0xAC; |
||||
|
sfr S3BUF = 0xAD; |
||||
|
sfr TA = 0xAE; |
||||
|
sfr IE2 = 0xAF; |
||||
|
sfr P3 = 0xB0; |
||||
|
sbit P30 = P3^0; |
||||
|
sbit P31 = P3^1; |
||||
|
sbit P32 = P3^2; |
||||
|
sbit P33 = P3^3; |
||||
|
sbit P34 = P3^4; |
||||
|
sbit P35 = P3^5; |
||||
|
sbit P36 = P3^6; |
||||
|
sbit P37 = P3^7; |
||||
|
sfr P3M1 = 0xB1; |
||||
|
sfr P3M0 = 0xB2; |
||||
|
sfr P4M1 = 0xB3; |
||||
|
sfr P4M0 = 0xB4; |
||||
|
sfr IP2 = 0xB5; |
||||
|
sfr IP2H = 0xB6; |
||||
|
sfr IPH = 0xB7; |
||||
|
sfr IP = 0xB8; |
||||
|
sbit PPCA = IP^7; |
||||
|
sbit PLVD = IP^6; |
||||
|
sbit PADC = IP^5; |
||||
|
sbit PS = IP^4; |
||||
|
sbit PT1 = IP^3; |
||||
|
sbit PX1 = IP^2; |
||||
|
sbit PT0 = IP^1; |
||||
|
sbit PX0 = IP^0; |
||||
|
sfr SADEN = 0xB9; |
||||
|
sfr P_SW2 = 0xBA; |
||||
|
sfr ADC_CONTR = 0xBC; |
||||
|
sfr ADC_RES = 0xBD; |
||||
|
sfr ADC_RESL = 0xBE; |
||||
|
sfr P4 = 0xC0; |
||||
|
sbit P40 = P4^0; |
||||
|
sbit P41 = P4^1; |
||||
|
sbit P42 = P4^2; |
||||
|
sbit P43 = P4^3; |
||||
|
sbit P44 = P4^4; |
||||
|
sbit P45 = P4^5; |
||||
|
sbit P46 = P4^6; |
||||
|
sbit P47 = P4^7; |
||||
|
sfr WDT_CONTR = 0xC1; |
||||
|
sfr IAP_DATA = 0xC2; |
||||
|
sfr IAP_ADDRH = 0xC3; |
||||
|
sfr IAP_ADDRL = 0xC4; |
||||
|
sfr IAP_CMD = 0xC5; |
||||
|
sfr IAP_TRIG = 0xC6; |
||||
|
sfr IAP_CONTR = 0xC7; |
||||
|
sfr P5 = 0xC8; |
||||
|
sbit P50 = P5^0; |
||||
|
sbit P51 = P5^1; |
||||
|
sbit P52 = P5^2; |
||||
|
sbit P53 = P5^3; |
||||
|
sbit P54 = P5^4; |
||||
|
sbit P55 = P5^5; |
||||
|
sbit P56 = P5^6; |
||||
|
sbit P57 = P5^7; |
||||
|
sfr P5M1 = 0xC9; |
||||
|
sfr P5M0 = 0xCA; |
||||
|
sfr SPSTAT = 0xCD; |
||||
|
sfr SPCTL = 0xCE; |
||||
|
sfr SPDAT = 0xCF; |
||||
|
sfr PSW = 0xD0; |
||||
|
sbit CY = PSW^7; |
||||
|
sbit AC = PSW^6; |
||||
|
sbit F0 = PSW^5; |
||||
|
sbit RS1 = PSW^4; |
||||
|
sbit RS0 = PSW^3; |
||||
|
sbit OV = PSW^2; |
||||
|
sbit P = PSW^0; |
||||
|
sfr T4T3M = 0xD1; |
||||
|
sfr T4H = 0xD2; |
||||
|
sfr T4L = 0xD3; |
||||
|
sfr T3H = 0xD4; |
||||
|
sfr T3L = 0xD5; |
||||
|
sfr T2H = 0xD6; |
||||
|
sfr T2L = 0xD7; |
||||
|
sfr CCON = 0xD8; |
||||
|
sbit CF = CCON^7; |
||||
|
sbit CR = CCON^6; |
||||
|
sbit CCF2 = CCON^2; |
||||
|
sbit CCF1 = CCON^1; |
||||
|
sbit CCF0 = CCON^0; |
||||
|
sfr CMOD = 0xD9; |
||||
|
sfr CCAPM0 = 0xDA; |
||||
|
sfr CCAPM1 = 0xDB; |
||||
|
sfr CCAPM2 = 0xDC; |
||||
|
sfr ADCCFG = 0xDE; |
||||
|
sfr IP3 = 0xDF; |
||||
|
sfr ACC = 0xE0; |
||||
|
sfr DPS = 0xE3; |
||||
|
sfr DPL1 = 0xE4; |
||||
|
sfr DPH1 = 0xE5; |
||||
|
sfr CMPCR1 = 0xE6; |
||||
|
sfr CMPCR2 = 0xE7; |
||||
|
sfr CL = 0xE9; |
||||
|
sfr CCAP0L = 0xEA; |
||||
|
sfr CCAP1L = 0xEB; |
||||
|
sfr CCAP2L = 0xEC; |
||||
|
sfr IP3H = 0xEE; |
||||
|
sfr AUXINTIF = 0xEF; |
||||
|
sfr B = 0xF0; |
||||
|
sfr PWMSET = 0xF1; |
||||
|
sfr PCA_PWM0 = 0xF2; |
||||
|
sfr PCA_PWM1 = 0xF3; |
||||
|
sfr PCA_PWM2 = 0xF4; |
||||
|
sfr IAP_TPS = 0xF5; |
||||
|
sfr PWMCFG01 = 0xF6; |
||||
|
sfr PWMCFG23 = 0xF7; |
||||
|
sfr CH = 0xF9; |
||||
|
sfr CCAP0H = 0xFA; |
||||
|
sfr CCAP1H = 0xFB; |
||||
|
sfr CCAP2H = 0xFC; |
||||
|
sfr PWMCFG45 = 0xFE; |
||||
|
sfr RSTCFG = 0xFF; |
||||
|
|
||||
|
//如下特殊功能寄存器位于扩展RAM区域
|
||||
|
//访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写
|
||||
|
|
||||
|
#define CKSEL (*(unsigned char volatile xdata *)0xFE00) |
||||
|
#define CLKDIV (*(unsigned char volatile xdata *)0xFE01) |
||||
|
#define HIRCCR (*(unsigned char volatile xdata *)0xFE02) |
||||
|
#define XOSCCR (*(unsigned char volatile xdata *)0xFE03) |
||||
|
#define IRC32KCR (*(unsigned char volatile xdata *)0xFE04) |
||||
|
#define MCLKOCR (*(unsigned char volatile xdata *)0xFE05) |
||||
|
#define IRCDB (*(unsigned char volatile xdata *)0xFE06) |
||||
|
|
||||
|
#define P0PU (*(unsigned char volatile xdata *)0xFE10) |
||||
|
#define P1PU (*(unsigned char volatile xdata *)0xFE11) |
||||
|
#define P2PU (*(unsigned char volatile xdata *)0xFE12) |
||||
|
#define P3PU (*(unsigned char volatile xdata *)0xFE13) |
||||
|
#define P4PU (*(unsigned char volatile xdata *)0xFE14) |
||||
|
#define P5PU (*(unsigned char volatile xdata *)0xFE15) |
||||
|
#define P0NCS (*(unsigned char volatile xdata *)0xFE18) |
||||
|
#define P1NCS (*(unsigned char volatile xdata *)0xFE19) |
||||
|
#define P2NCS (*(unsigned char volatile xdata *)0xFE1A) |
||||
|
#define P3NCS (*(unsigned char volatile xdata *)0xFE1B) |
||||
|
#define P4NCS (*(unsigned char volatile xdata *)0xFE1C) |
||||
|
#define P5NCS (*(unsigned char volatile xdata *)0xFE1D) |
||||
|
#define P0SR (*(unsigned char volatile xdata *)0xFE20) |
||||
|
#define P1SR (*(unsigned char volatile xdata *)0xFE21) |
||||
|
#define P2SR (*(unsigned char volatile xdata *)0xFE22) |
||||
|
#define P3SR (*(unsigned char volatile xdata *)0xFE23) |
||||
|
#define P4SR (*(unsigned char volatile xdata *)0xFE24) |
||||
|
#define P5SR (*(unsigned char volatile xdata *)0xFE25) |
||||
|
#define P0DR (*(unsigned char volatile xdata *)0xFE28) |
||||
|
#define P1DR (*(unsigned char volatile xdata *)0xFE29) |
||||
|
#define P2DR (*(unsigned char volatile xdata *)0xFE2A) |
||||
|
#define P3DR (*(unsigned char volatile xdata *)0xFE2B) |
||||
|
#define P4DR (*(unsigned char volatile xdata *)0xFE2C) |
||||
|
#define P5DR (*(unsigned char volatile xdata *)0xFE2D) |
||||
|
#define P0IE (*(unsigned char volatile xdata *)0xFE30) |
||||
|
#define P1IE (*(unsigned char volatile xdata *)0xFE31) |
||||
|
#define P3IE (*(unsigned char volatile xdata *)0xFE33) |
||||
|
|
||||
|
#define I2CCFG (*(unsigned char volatile xdata *)0xFE80) |
||||
|
#define I2CMSCR (*(unsigned char volatile xdata *)0xFE81) |
||||
|
#define I2CMSST (*(unsigned char volatile xdata *)0xFE82) |
||||
|
#define I2CSLCR (*(unsigned char volatile xdata *)0xFE83) |
||||
|
#define I2CSLST (*(unsigned char volatile xdata *)0xFE84) |
||||
|
#define I2CSLADR (*(unsigned char volatile xdata *)0xFE85) |
||||
|
#define I2CTXD (*(unsigned char volatile xdata *)0xFE86) |
||||
|
#define I2CRXD (*(unsigned char volatile xdata *)0xFE87) |
||||
|
#define I2CMSAUX (*(unsigned char volatile xdata *)0xFE88) |
||||
|
|
||||
|
#define TM2PS (*(unsigned char volatile xdata *)0xFEA2) |
||||
|
#define TM3PS (*(unsigned char volatile xdata *)0xFEA3) |
||||
|
#define TM4PS (*(unsigned char volatile xdata *)0xFEA4) |
||||
|
#define ADCTIM (*(unsigned char volatile xdata *)0xFEA8) |
||||
|
|
||||
|
#define PWM0CH (*(unsigned char volatile xdata *)0xFF00) |
||||
|
#define PWM0CL (*(unsigned char volatile xdata *)0xFF01) |
||||
|
#define PWM0CKS (*(unsigned char volatile xdata *)0xFF02) |
||||
|
#define PWM0TADCH (*(unsigned char volatile xdata *)0xFF03) |
||||
|
#define PWM0TADCL (*(unsigned char volatile xdata *)0xFF04) |
||||
|
#define PWM0IF (*(unsigned char volatile xdata *)0xFF05) |
||||
|
#define PWM0FDCR (*(unsigned char volatile xdata *)0xFF06) |
||||
|
#define PWM00T1H (*(unsigned char volatile xdata *)0xFF10) |
||||
|
#define PWM00T1L (*(unsigned char volatile xdata *)0xFF11) |
||||
|
#define PWM00T2H (*(unsigned char volatile xdata *)0xFF12) |
||||
|
#define PWM00T2L (*(unsigned char volatile xdata *)0xFF13) |
||||
|
#define PWM00CR (*(unsigned char volatile xdata *)0xFF14) |
||||
|
#define PWM00HLD (*(unsigned char volatile xdata *)0xFF15) |
||||
|
#define PWM01T1H (*(unsigned char volatile xdata *)0xFF18) |
||||
|
#define PWM01T1L (*(unsigned char volatile xdata *)0xFF19) |
||||
|
#define PWM01T2H (*(unsigned char volatile xdata *)0xFF1A) |
||||
|
#define PWM01T2L (*(unsigned char volatile xdata *)0xFF1B) |
||||
|
#define PWM01CR (*(unsigned char volatile xdata *)0xFF1C) |
||||
|
#define PWM01HLD (*(unsigned char volatile xdata *)0xFF1D) |
||||
|
#define PWM02T1H (*(unsigned char volatile xdata *)0xFF20) |
||||
|
#define PWM02T1L (*(unsigned char volatile xdata *)0xFF21) |
||||
|
#define PWM02T2H (*(unsigned char volatile xdata *)0xFF22) |
||||
|
#define PWM02T2L (*(unsigned char volatile xdata *)0xFF23) |
||||
|
#define PWM02CR (*(unsigned char volatile xdata *)0xFF24) |
||||
|
#define PWM02HLD (*(unsigned char volatile xdata *)0xFF25) |
||||
|
#define PWM03T1H (*(unsigned char volatile xdata *)0xFF28) |
||||
|
#define PWM03T1L (*(unsigned char volatile xdata *)0xFF29) |
||||
|
#define PWM03T2H (*(unsigned char volatile xdata *)0xFF2A) |
||||
|
#define PWM03T2L (*(unsigned char volatile xdata *)0xFF2B) |
||||
|
#define PWM03CR (*(unsigned char volatile xdata *)0xFF2C) |
||||
|
#define PWM03HLD (*(unsigned char volatile xdata *)0xFF2D) |
||||
|
#define PWM04T1H (*(unsigned char volatile xdata *)0xFF30) |
||||
|
#define PWM04T1L (*(unsigned char volatile xdata *)0xFF31) |
||||
|
#define PWM04T2H (*(unsigned char volatile xdata *)0xFF32) |
||||
|
#define PWM04T2L (*(unsigned char volatile xdata *)0xFF33) |
||||
|
#define PWM04CR (*(unsigned char volatile xdata *)0xFF34) |
||||
|
#define PWM04HLD (*(unsigned char volatile xdata *)0xFF35) |
||||
|
#define PWM05T1H (*(unsigned char volatile xdata *)0xFF38) |
||||
|
#define PWM05T1L (*(unsigned char volatile xdata *)0xFF39) |
||||
|
#define PWM05T2H (*(unsigned char volatile xdata *)0xFF3A) |
||||
|
#define PWM05T2L (*(unsigned char volatile xdata *)0xFF3B) |
||||
|
#define PWM05CR (*(unsigned char volatile xdata *)0xFF3C) |
||||
|
#define PWM05HLD (*(unsigned char volatile xdata *)0xFF3D) |
||||
|
#define PWM06T1H (*(unsigned char volatile xdata *)0xFF40) |
||||
|
#define PWM06T1L (*(unsigned char volatile xdata *)0xFF41) |
||||
|
#define PWM06T2H (*(unsigned char volatile xdata *)0xFF42) |
||||
|
#define PWM06T2L (*(unsigned char volatile xdata *)0xFF43) |
||||
|
#define PWM06CR (*(unsigned char volatile xdata *)0xFF44) |
||||
|
#define PWM06HLD (*(unsigned char volatile xdata *)0xFF45) |
||||
|
#define PWM07T1H (*(unsigned char volatile xdata *)0xFF48) |
||||
|
#define PWM07T1L (*(unsigned char volatile xdata *)0xFF49) |
||||
|
#define PWM07T2H (*(unsigned char volatile xdata *)0xFF4A) |
||||
|
#define PWM07T2L (*(unsigned char volatile xdata *)0xFF4B) |
||||
|
#define PWM07CR (*(unsigned char volatile xdata *)0xFF4C) |
||||
|
#define PWM07HLD (*(unsigned char volatile xdata *)0xFF4D) |
||||
|
#define PWM1CH (*(unsigned char volatile xdata *)0xFF50) |
||||
|
#define PWM1CL (*(unsigned char volatile xdata *)0xFF51) |
||||
|
#define PWM1CKS (*(unsigned char volatile xdata *)0xFF52) |
||||
|
#define PWM1IF (*(unsigned char volatile xdata *)0xFF55) |
||||
|
#define PWM1FDCR (*(unsigned char volatile xdata *)0xFF56) |
||||
|
#define PWM10T1H (*(unsigned char volatile xdata *)0xFF60) |
||||
|
#define PWM10T1L (*(unsigned char volatile xdata *)0xFF61) |
||||
|
#define PWM10T2H (*(unsigned char volatile xdata *)0xFF62) |
||||
|
#define PWM10T2L (*(unsigned char volatile xdata *)0xFF63) |
||||
|
#define PWM10CR (*(unsigned char volatile xdata *)0xFF64) |
||||
|
#define PWM10HLD (*(unsigned char volatile xdata *)0xFF65) |
||||
|
#define PWM11T1H (*(unsigned char volatile xdata *)0xFF68) |
||||
|
#define PWM11T1L (*(unsigned char volatile xdata *)0xFF69) |
||||
|
#define PWM11T2H (*(unsigned char volatile xdata *)0xFF6A) |
||||
|
#define PWM11T2L (*(unsigned char volatile xdata *)0xFF6B) |
||||
|
#define PWM11CR (*(unsigned char volatile xdata *)0xFF6C) |
||||
|
#define PWM11HLD (*(unsigned char volatile xdata *)0xFF6D) |
||||
|
#define PWM12T1H (*(unsigned char volatile xdata *)0xFF70) |
||||
|
#define PWM12T1L (*(unsigned char volatile xdata *)0xFF71) |
||||
|
#define PWM12T2H (*(unsigned char volatile xdata *)0xFF72) |
||||
|
#define PWM12T2L (*(unsigned char volatile xdata *)0xFF73) |
||||
|
#define PWM12CR (*(unsigned char volatile xdata *)0xFF74) |
||||
|
#define PWM12HLD (*(unsigned char volatile xdata *)0xFF75) |
||||
|
#define PWM13T1H (*(unsigned char volatile xdata *)0xFF78) |
||||
|
#define PWM13T1L (*(unsigned char volatile xdata *)0xFF79) |
||||
|
#define PWM13T2H (*(unsigned char volatile xdata *)0xFF7A) |
||||
|
#define PWM13T2L (*(unsigned char volatile xdata *)0xFF7B) |
||||
|
#define PWM13CR (*(unsigned char volatile xdata *)0xFF7C) |
||||
|
#define PWM13HLD (*(unsigned char volatile xdata *)0xFF7D) |
||||
|
#define PWM14T1H (*(unsigned char volatile xdata *)0xFF80) |
||||
|
#define PWM14T1L (*(unsigned char volatile xdata *)0xFF81) |
||||
|
#define PWM14T2H (*(unsigned char volatile xdata *)0xFF82) |
||||
|
#define PWM14T2L (*(unsigned char volatile xdata *)0xFF83) |
||||
|
#define PWM14CR (*(unsigned char volatile xdata *)0xFF84) |
||||
|
#define PWM14HLD (*(unsigned char volatile xdata *)0xFF85) |
||||
|
#define PWM15T1H (*(unsigned char volatile xdata *)0xFF88) |
||||
|
#define PWM15T1L (*(unsigned char volatile xdata *)0xFF89) |
||||
|
#define PWM15T2H (*(unsigned char volatile xdata *)0xFF8A) |
||||
|
#define PWM15T2L (*(unsigned char volatile xdata *)0xFF8B) |
||||
|
#define PWM15CR (*(unsigned char volatile xdata *)0xFF8C) |
||||
|
#define PWM15HLD (*(unsigned char volatile xdata *)0xFF8D) |
||||
|
#define PWM16T1H (*(unsigned char volatile xdata *)0xFF90) |
||||
|
#define PWM16T1L (*(unsigned char volatile xdata *)0xFF91) |
||||
|
#define PWM16T2H (*(unsigned char volatile xdata *)0xFF92) |
||||
|
#define PWM16T2L (*(unsigned char volatile xdata *)0xFF93) |
||||
|
#define PWM16CR (*(unsigned char volatile xdata *)0xFF94) |
||||
|
#define PWM16HLD (*(unsigned char volatile xdata *)0xFF95) |
||||
|
#define PWM17T1H (*(unsigned char volatile xdata *)0xFF98) |
||||
|
#define PWM17T1L (*(unsigned char volatile xdata *)0xFF99) |
||||
|
#define PWM17T2H (*(unsigned char volatile xdata *)0xFF9A) |
||||
|
#define PWM17T2L (*(unsigned char volatile xdata *)0xFF9B) |
||||
|
#define PWM17CR (*(unsigned char volatile xdata *)0xFF9C) |
||||
|
#define PWM17HLD (*(unsigned char volatile xdata *)0xFF9D) |
||||
|
#define PWM2CH (*(unsigned char volatile xdata *)0xFFA0) |
||||
|
#define PWM2CL (*(unsigned char volatile xdata *)0xFFA1) |
||||
|
#define PWM2CKS (*(unsigned char volatile xdata *)0xFFA2) |
||||
|
#define PWM2TADCH (*(unsigned char volatile xdata *)0xFFA3) |
||||
|
#define PWM2TADCL (*(unsigned char volatile xdata *)0xFFA4) |
||||
|
#define PWM2IF (*(unsigned char volatile xdata *)0xFFA5) |
||||
|
#define PWM2FDCR (*(unsigned char volatile xdata *)0xFFA6) |
||||
|
#define PWM20T1H (*(unsigned char volatile xdata *)0xFFB0) |
||||
|
#define PWM20T1L (*(unsigned char volatile xdata *)0xFFB1) |
||||
|
#define PWM20T2H (*(unsigned char volatile xdata *)0xFFB2) |
||||
|
#define PWM20T2L (*(unsigned char volatile xdata *)0xFFB3) |
||||
|
#define PWM20CR (*(unsigned char volatile xdata *)0xFFB4) |
||||
|
#define PWM20HLD (*(unsigned char volatile xdata *)0xFFB5) |
||||
|
#define PWM21T1H (*(unsigned char volatile xdata *)0xFFB8) |
||||
|
#define PWM21T1L (*(unsigned char volatile xdata *)0xFFB9) |
||||
|
#define PWM21T2H (*(unsigned char volatile xdata *)0xFFBA) |
||||
|
#define PWM21T2L (*(unsigned char volatile xdata *)0xFFBB) |
||||
|
#define PWM21CR (*(unsigned char volatile xdata *)0xFFBC) |
||||
|
#define PWM21HLD (*(unsigned char volatile xdata *)0xFFBD) |
||||
|
#define PWM22T1H (*(unsigned char volatile xdata *)0xFFC0) |
||||
|
#define PWM22T1L (*(unsigned char volatile xdata *)0xFFC1) |
||||
|
#define PWM22T2H (*(unsigned char volatile xdata *)0xFFC2) |
||||
|
#define PWM22T2L (*(unsigned char volatile xdata *)0xFFC3) |
||||
|
#define PWM22CR (*(unsigned char volatile xdata *)0xFFC4) |
||||
|
#define PWM22HLD (*(unsigned char volatile xdata *)0xFFC5) |
||||
|
#define PWM23T1H (*(unsigned char volatile xdata *)0xFFC8) |
||||
|
#define PWM23T1L (*(unsigned char volatile xdata *)0xFFC9) |
||||
|
#define PWM23T2H (*(unsigned char volatile xdata *)0xFFCA) |
||||
|
#define PWM23T2L (*(unsigned char volatile xdata *)0xFFCB) |
||||
|
#define PWM23CR (*(unsigned char volatile xdata *)0xFFCC) |
||||
|
#define PWM23HLD (*(unsigned char volatile xdata *)0xFFCD) |
||||
|
#define PWM24T1H (*(unsigned char volatile xdata *)0xFFD0) |
||||
|
#define PWM24T1L (*(unsigned char volatile xdata *)0xFFD1) |
||||
|
#define PWM24T2H (*(unsigned char volatile xdata *)0xFFD2) |
||||
|
#define PWM24T2L (*(unsigned char volatile xdata *)0xFFD3) |
||||
|
#define PWM24CR (*(unsigned char volatile xdata *)0xFFD4) |
||||
|
#define PWM24HLD (*(unsigned char volatile xdata *)0xFFD5) |
||||
|
#define PWM25T1H (*(unsigned char volatile xdata *)0xFFD8) |
||||
|
#define PWM25T1L (*(unsigned char volatile xdata *)0xFFD9) |
||||
|
#define PWM25T2H (*(unsigned char volatile xdata *)0xFFDA) |
||||
|
#define PWM25T2L (*(unsigned char volatile xdata *)0xFFDB) |
||||
|
#define PWM25CR (*(unsigned char volatile xdata *)0xFFDC) |
||||
|
#define PWM25HLD (*(unsigned char volatile xdata *)0xFFDD) |
||||
|
#define PWM26T1H (*(unsigned char volatile xdata *)0xFFE0) |
||||
|
#define PWM26T1L (*(unsigned char volatile xdata *)0xFFE1) |
||||
|
#define PWM26T2H (*(unsigned char volatile xdata *)0xFFE2) |
||||
|
#define PWM26T2L (*(unsigned char volatile xdata *)0xFFE3) |
||||
|
#define PWM26CR (*(unsigned char volatile xdata *)0xFFE4) |
||||
|
#define PWM26HLD (*(unsigned char volatile xdata *)0xFFE5) |
||||
|
#define PWM27T1H (*(unsigned char volatile xdata *)0xFFE8) |
||||
|
#define PWM27T1L (*(unsigned char volatile xdata *)0xFFE9) |
||||
|
#define PWM27T2H (*(unsigned char volatile xdata *)0xFFEA) |
||||
|
#define PWM27T2L (*(unsigned char volatile xdata *)0xFFEB) |
||||
|
#define PWM27CR (*(unsigned char volatile xdata *)0xFFEC) |
||||
|
#define PWM27HLD (*(unsigned char volatile xdata *)0xFFED) |
||||
|
#define PWM3CH (*(unsigned char volatile xdata *)0xFC00) |
||||
|
#define PWM3CL (*(unsigned char volatile xdata *)0xFC01) |
||||
|
#define PWM3CKS (*(unsigned char volatile xdata *)0xFC02) |
||||
|
#define PWM3IF (*(unsigned char volatile xdata *)0xFC05) |
||||
|
#define PWM3FDCR (*(unsigned char volatile xdata *)0xFC06) |
||||
|
#define PWM30T1H (*(unsigned char volatile xdata *)0xFC10) |
||||
|
#define PWM30T1L (*(unsigned char volatile xdata *)0xFC11) |
||||
|
#define PWM30T2H (*(unsigned char volatile xdata *)0xFC12) |
||||
|
#define PWM30T2L (*(unsigned char volatile xdata *)0xFC13) |
||||
|
#define PWM30CR (*(unsigned char volatile xdata *)0xFC14) |
||||
|
#define PWM30HLD (*(unsigned char volatile xdata *)0xFC15) |
||||
|
#define PWM31T1H (*(unsigned char volatile xdata *)0xFC18) |
||||
|
#define PWM31T1L (*(unsigned char volatile xdata *)0xFC19) |
||||
|
#define PWM31T2H (*(unsigned char volatile xdata *)0xFC1A) |
||||
|
#define PWM31T2L (*(unsigned char volatile xdata *)0xFC1B) |
||||
|
#define PWM31CR (*(unsigned char volatile xdata *)0xFC1C) |
||||
|
#define PWM31HLD (*(unsigned char volatile xdata *)0xFC1D) |
||||
|
#define PWM32T1H (*(unsigned char volatile xdata *)0xFC20) |
||||
|
#define PWM32T1L (*(unsigned char volatile xdata *)0xFC21) |
||||
|
#define PWM32T2H (*(unsigned char volatile xdata *)0xFC22) |
||||
|
#define PWM32T2L (*(unsigned char volatile xdata *)0xFC23) |
||||
|
#define PWM32CR (*(unsigned char volatile xdata *)0xFC24) |
||||
|
#define PWM32HLD (*(unsigned char volatile xdata *)0xFC25) |
||||
|
#define PWM33T1H (*(unsigned char volatile xdata *)0xFC28) |
||||
|
#define PWM33T1L (*(unsigned char volatile xdata *)0xFC29) |
||||
|
#define PWM33T2H (*(unsigned char volatile xdata *)0xFC2A) |
||||
|
#define PWM33T2L (*(unsigned char volatile xdata *)0xFC2B) |
||||
|
#define PWM33CR (*(unsigned char volatile xdata *)0xFC2C) |
||||
|
#define PWM33HLD (*(unsigned char volatile xdata *)0xFC2D) |
||||
|
#define PWM34T1H (*(unsigned char volatile xdata *)0xFC30) |
||||
|
#define PWM34T1L (*(unsigned char volatile xdata *)0xFC31) |
||||
|
#define PWM34T2H (*(unsigned char volatile xdata *)0xFC32) |
||||
|
#define PWM34T2L (*(unsigned char volatile xdata *)0xFC33) |
||||
|
#define PWM34CR (*(unsigned char volatile xdata *)0xFC34) |
||||
|
#define PWM34HLD (*(unsigned char volatile xdata *)0xFC35) |
||||
|
#define PWM35T1H (*(unsigned char volatile xdata *)0xFC38) |
||||
|
#define PWM35T1L (*(unsigned char volatile xdata *)0xFC39) |
||||
|
#define PWM35T2H (*(unsigned char volatile xdata *)0xFC3A) |
||||
|
#define PWM35T2L (*(unsigned char volatile xdata *)0xFC3B) |
||||
|
#define PWM35CR (*(unsigned char volatile xdata *)0xFC3C) |
||||
|
#define PWM35HLD (*(unsigned char volatile xdata *)0xFC3D) |
||||
|
#define PWM36T1H (*(unsigned char volatile xdata *)0xFC40) |
||||
|
#define PWM36T1L (*(unsigned char volatile xdata *)0xFC41) |
||||
|
#define PWM36T2H (*(unsigned char volatile xdata *)0xFC42) |
||||
|
#define PWM36T2L (*(unsigned char volatile xdata *)0xFC43) |
||||
|
#define PWM36CR (*(unsigned char volatile xdata *)0xFC44) |
||||
|
#define PWM36HLD (*(unsigned char volatile xdata *)0xFC45) |
||||
|
#define PWM37T1H (*(unsigned char volatile xdata *)0xFC48) |
||||
|
#define PWM37T1L (*(unsigned char volatile xdata *)0xFC49) |
||||
|
#define PWM37T2H (*(unsigned char volatile xdata *)0xFC4A) |
||||
|
#define PWM37T2L (*(unsigned char volatile xdata *)0xFC4B) |
||||
|
#define PWM37CR (*(unsigned char volatile xdata *)0xFC4C) |
||||
|
#define PWM37HLD (*(unsigned char volatile xdata *)0xFC4D) |
||||
|
#define PWM4CH (*(unsigned char volatile xdata *)0xFC50) |
||||
|
#define PWM4CL (*(unsigned char volatile xdata *)0xFC51) |
||||
|
#define PWM4CKS (*(unsigned char volatile xdata *)0xFC52) |
||||
|
#define PWM4TADCH (*(unsigned char volatile xdata *)0xFC53) |
||||
|
#define PWM4TADCL (*(unsigned char volatile xdata *)0xFC54) |
||||
|
#define PWM4IF (*(unsigned char volatile xdata *)0xFC55) |
||||
|
#define PWM4FDCR (*(unsigned char volatile xdata *)0xFC56) |
||||
|
#define PWM40T1H (*(unsigned char volatile xdata *)0xFC60) |
||||
|
#define PWM40T1L (*(unsigned char volatile xdata *)0xFC61) |
||||
|
#define PWM40T2H (*(unsigned char volatile xdata *)0xFC62) |
||||
|
#define PWM40T2L (*(unsigned char volatile xdata *)0xFC63) |
||||
|
#define PWM40CR (*(unsigned char volatile xdata *)0xFC64) |
||||
|
#define PWM40HLD (*(unsigned char volatile xdata *)0xFC65) |
||||
|
#define PWM41T1H (*(unsigned char volatile xdata *)0xFC68) |
||||
|
#define PWM41T1L (*(unsigned char volatile xdata *)0xFC69) |
||||
|
#define PWM41T2H (*(unsigned char volatile xdata *)0xFC6A) |
||||
|
#define PWM41T2L (*(unsigned char volatile xdata *)0xFC6B) |
||||
|
#define PWM41CR (*(unsigned char volatile xdata *)0xFC6C) |
||||
|
#define PWM41HLD (*(unsigned char volatile xdata *)0xFC6D) |
||||
|
#define PWM42T1H (*(unsigned char volatile xdata *)0xFC70) |
||||
|
#define PWM42T1L (*(unsigned char volatile xdata *)0xFC71) |
||||
|
#define PWM42T2H (*(unsigned char volatile xdata *)0xFC72) |
||||
|
#define PWM42T2L (*(unsigned char volatile xdata *)0xFC73) |
||||
|
#define PWM42CR (*(unsigned char volatile xdata *)0xFC74) |
||||
|
#define PWM42HLD (*(unsigned char volatile xdata *)0xFC75) |
||||
|
#define PWM43T1H (*(unsigned char volatile xdata *)0xFC78) |
||||
|
#define PWM43T1L (*(unsigned char volatile xdata *)0xFC79) |
||||
|
#define PWM43T2H (*(unsigned char volatile xdata *)0xFC7A) |
||||
|
#define PWM43T2L (*(unsigned char volatile xdata *)0xFC7B) |
||||
|
#define PWM43CR (*(unsigned char volatile xdata *)0xFC7C) |
||||
|
#define PWM43HLD (*(unsigned char volatile xdata *)0xFC7D) |
||||
|
#define PWM44T1H (*(unsigned char volatile xdata *)0xFC80) |
||||
|
#define PWM44T1L (*(unsigned char volatile xdata *)0xFC81) |
||||
|
#define PWM44T2H (*(unsigned char volatile xdata *)0xFC82) |
||||
|
#define PWM44T2L (*(unsigned char volatile xdata *)0xFC83) |
||||
|
#define PWM44CR (*(unsigned char volatile xdata *)0xFC84) |
||||
|
#define PWM44HLD (*(unsigned char volatile xdata *)0xFC85) |
||||
|
#define PWM45T1H (*(unsigned char volatile xdata *)0xFC88) |
||||
|
#define PWM45T1L (*(unsigned char volatile xdata *)0xFC89) |
||||
|
#define PWM45T2H (*(unsigned char volatile xdata *)0xFC8A) |
||||
|
#define PWM45T2L (*(unsigned char volatile xdata *)0xFC8B) |
||||
|
#define PWM45CR (*(unsigned char volatile xdata *)0xFC8C) |
||||
|
#define PWM45HLD (*(unsigned char volatile xdata *)0xFC8D) |
||||
|
#define PWM46T1H (*(unsigned char volatile xdata *)0xFC90) |
||||
|
#define PWM46T1L (*(unsigned char volatile xdata *)0xFC91) |
||||
|
#define PWM46T2H (*(unsigned char volatile xdata *)0xFC92) |
||||
|
#define PWM46T2L (*(unsigned char volatile xdata *)0xFC93) |
||||
|
#define PWM46CR (*(unsigned char volatile xdata *)0xFC94) |
||||
|
#define PWM46HLD (*(unsigned char volatile xdata *)0xFC95) |
||||
|
#define PWM47T1H (*(unsigned char volatile xdata *)0xFC98) |
||||
|
#define PWM47T1L (*(unsigned char volatile xdata *)0xFC99) |
||||
|
#define PWM47T2H (*(unsigned char volatile xdata *)0xFC9A) |
||||
|
#define PWM47T2L (*(unsigned char volatile xdata *)0xFC9B) |
||||
|
#define PWM47CR (*(unsigned char volatile xdata *)0xFC9C) |
||||
|
#define PWM47HLD (*(unsigned char volatile xdata *)0xFC9D) |
||||
|
#define PWM5CH (*(unsigned char volatile xdata *)0xFCA0) |
||||
|
#define PWM5CL (*(unsigned char volatile xdata *)0xFCA1) |
||||
|
#define PWM5CKS (*(unsigned char volatile xdata *)0xFCA2) |
||||
|
#define PWM5IF (*(unsigned char volatile xdata *)0xFCA5) |
||||
|
#define PWM5FDCR (*(unsigned char volatile xdata *)0xFCA6) |
||||
|
#define PWM50T1H (*(unsigned char volatile xdata *)0xFCB0) |
||||
|
#define PWM50T1L (*(unsigned char volatile xdata *)0xFCB1) |
||||
|
#define PWM50T2H (*(unsigned char volatile xdata *)0xFCB2) |
||||
|
#define PWM50T2L (*(unsigned char volatile xdata *)0xFCB3) |
||||
|
#define PWM50CR (*(unsigned char volatile xdata *)0xFCB4) |
||||
|
#define PWM50HLD (*(unsigned char volatile xdata *)0xFCB5) |
||||
|
#define PWM51T1H (*(unsigned char volatile xdata *)0xFCB8) |
||||
|
#define PWM51T1L (*(unsigned char volatile xdata *)0xFCB9) |
||||
|
#define PWM51T2H (*(unsigned char volatile xdata *)0xFCBA) |
||||
|
#define PWM51T2L (*(unsigned char volatile xdata *)0xFCBB) |
||||
|
#define PWM51CR (*(unsigned char volatile xdata *)0xFCBC) |
||||
|
#define PWM51HLD (*(unsigned char volatile xdata *)0xFCBD) |
||||
|
#define PWM52T1H (*(unsigned char volatile xdata *)0xFCC0) |
||||
|
#define PWM52T1L (*(unsigned char volatile xdata *)0xFCC1) |
||||
|
#define PWM52T2H (*(unsigned char volatile xdata *)0xFCC2) |
||||
|
#define PWM52T2L (*(unsigned char volatile xdata *)0xFCC3) |
||||
|
#define PWM52CR (*(unsigned char volatile xdata *)0xFCC4) |
||||
|
#define PWM52HLD (*(unsigned char volatile xdata *)0xFCC5) |
||||
|
#define PWM53T1H (*(unsigned char volatile xdata *)0xFCC8) |
||||
|
#define PWM53T1L (*(unsigned char volatile xdata *)0xFCC9) |
||||
|
#define PWM53T2H (*(unsigned char volatile xdata *)0xFCCA) |
||||
|
#define PWM53T2L (*(unsigned char volatile xdata *)0xFCCB) |
||||
|
#define PWM53CR (*(unsigned char volatile xdata *)0xFCCC) |
||||
|
#define PWM53HLD (*(unsigned char volatile xdata *)0xFCCD) |
||||
|
#define PWM54T1H (*(unsigned char volatile xdata *)0xFCD0) |
||||
|
#define PWM54T1L (*(unsigned char volatile xdata *)0xFCD1) |
||||
|
#define PWM54T2H (*(unsigned char volatile xdata *)0xFCD2) |
||||
|
#define PWM54T2L (*(unsigned char volatile xdata *)0xFCD3) |
||||
|
#define PWM54CR (*(unsigned char volatile xdata *)0xFCD4) |
||||
|
#define PWM54HLD (*(unsigned char volatile xdata *)0xFCD5) |
||||
|
#define PWM55T1H (*(unsigned char volatile xdata *)0xFCD8) |
||||
|
#define PWM55T1L (*(unsigned char volatile xdata *)0xFCD9) |
||||
|
#define PWM55T2H (*(unsigned char volatile xdata *)0xFCDA) |
||||
|
#define PWM55T2L (*(unsigned char volatile xdata *)0xFCDB) |
||||
|
#define PWM55CR (*(unsigned char volatile xdata *)0xFCDC) |
||||
|
#define PWM55HLD (*(unsigned char volatile xdata *)0xFCDD) |
||||
|
#define PWM56T1H (*(unsigned char volatile xdata *)0xFCE0) |
||||
|
#define PWM56T1L (*(unsigned char volatile xdata *)0xFCE1) |
||||
|
#define PWM56T2H (*(unsigned char volatile xdata *)0xFCE2) |
||||
|
#define PWM56T2L (*(unsigned char volatile xdata *)0xFCE3) |
||||
|
#define PWM56CR (*(unsigned char volatile xdata *)0xFCE4) |
||||
|
#define PWM56HLD (*(unsigned char volatile xdata *)0xFCE5) |
||||
|
#define PWM57T1H (*(unsigned char volatile xdata *)0xFCE8) |
||||
|
#define PWM57T1L (*(unsigned char volatile xdata *)0xFCE9) |
||||
|
#define PWM57T2H (*(unsigned char volatile xdata *)0xFCEA) |
||||
|
#define PWM57T2L (*(unsigned char volatile xdata *)0xFCEB) |
||||
|
#define PWM57CR (*(unsigned char volatile xdata *)0xFCEC) |
||||
|
#define PWM57HLD (*(unsigned char volatile xdata *)0xFCED) |
||||
|
|
||||
|
/////////////////////////////////////////////////
|
||||
|
|
||||
|
|
||||
|
/// >>>>> add by cc
|
||||
|
|
||||
|
#include "../clib/bit.h" |
||||
|
|
||||
|
#define D_stdIO_P0_ALL() P0M1=0;P0M0=0; |
||||
|
#define D_HighI_P0_ALL() P0M1=0;P0M0=0XFF; |
||||
|
#define D_HighR_P0_ALL() P0M1=0XFF;P0M0=0; |
||||
|
#define D_OpenD_P0_ALL() P0M1=0XFF;P0M0=0XFF; |
||||
|
|
||||
|
#define D_stdIO_P1_ALL() P1M1=0;P1M0=0; |
||||
|
#define D_HighI_P1_ALL() P1M1=0;P1M0=0XFF; |
||||
|
#define D_HighR_P1_ALL() P1M1=0XFF;P1M0=0; |
||||
|
#define D_OpenD_P1_ALL() P1M1=0XFF;P1M0=0XFF; |
||||
|
|
||||
|
|
||||
|
#define D_stdIO_P0(n) BITN_0(P0M1,n);BITN_0(P0M0,n); //////00 准双向口 灌电流20mA 拉电流270-150uS
|
||||
|
#define D_HighI_P0(n) BITN_0(P0M1,n);BITN_1(P0M0,n); //////01 推挽输出 20mA 加限流
|
||||
|
#define D_HighR_P0(n) BITN_1(P0M1,n);BITN_0(P0M0,n); /////////10 高阻
|
||||
|
#define D_OpenD_P0(n) BITN_1(P0M1,n);BITN_1(P0M0,n); /////11 开漏 open-Drain 内部上拉电阻断开 开漏模式既可以度外部状态也可以对外输出高低电平
|
||||
|
|
||||
|
#define D_stdIO_P1(n) BITN_0(P1M1,n);BITN_0(P1M0,n); //////00 准双向口 灌电流20mA 拉电流270-150uS
|
||||
|
#define D_HighI_P1(n) BITN_0(P1M1,n);BITN_1(P1M0,n); //////01 推挽输出 20mA 加限流
|
||||
|
#define D_HighR_P1(n) BITN_1(P1M1,n);BITN_0(P1M0,n); /////////10 高阻
|
||||
|
#define D_OpenD_P1(n) BITN_1(P1M1,n);BITN_1(P1M0,n); /////11 开漏 open-Drain 内部上拉电阻断开 开漏模式既可以度外部状态也可以对外输出高低电平
|
||||
|
|
||||
|
#define D_stdIO_P2(n) BITN_0(P2M1,n);BITN_0(P2M0,n); //////00 准双向口 灌电流20mA 拉电流270-150uS
|
||||
|
#define D_HighI_P2(n) BITN_0(P2M1,n);BITN_1(P2M0,n); //////01 推挽输出 20mA 加限流
|
||||
|
#define D_HighR_P2(n) BITN_1(P2M1,n);BITN_0(P2M0,n); /////////10 高阻
|
||||
|
#define D_OpenD_P2(n) BITN_1(P2M1,n);BITN_1(P2M0,n); /////11 开漏 open-Drain 内部上拉电阻断开 开漏模式既可以度外部状态也可以对外输出高低电平
|
||||
|
|
||||
|
#define D_stdIO_P3(n) BITN_0(P3M1,n);BITN_0(P3M0,n); //////00 准双向口 灌电流20mA 拉电流270-150uS
|
||||
|
#define D_HighI_P3(n) BITN_0(P3M1,n);BITN_1(P3M0,n); //////01 推挽输出 20mA 加限流
|
||||
|
#define D_HighR_P3(n) BITN_1(P3M1,n);BITN_0(P3M0,n); /////////10 高阻
|
||||
|
#define D_OpenD_P3(n) BITN_1(P3M1,n);BITN_1(P3M0,n); /////11 开漏 open-Drain 内部上拉电阻断开 开漏模式既可以度外部状态也可以对外输出高低电平
|
||||
|
|
||||
|
#define D_stdIO_P4(n) BITN_0(P4M1,n);BITN_0(P4M0,n); //////00 准双向口 灌电流20mA 拉电流270-150uS
|
||||
|
#define D_HighI_P4(n) BITN_0(P4M1,n);BITN_1(P4M0,n); //////01 推挽输出 20mA 加限流
|
||||
|
#define D_HighR_P4(n) BITN_1(P4M1,n);BITN_0(P4M0,n); /////////10 高阻
|
||||
|
#define D_OpenD_P4(n) BITN_1(P4M1,n);BITN_1(P4M0,n); /////11 开漏 open-Drain 内部上拉电阻断开 开漏模式既可以度外部状态也可以对外输出高低电平
|
||||
|
|
||||
|
#define D_stdIO_P5(n) BITN_0(P5M1,n);BITN_0(P5M0,n); //////00 准双向口 灌电流20mA 拉电流270-150uS
|
||||
|
#define D_HighI_P5(n) BITN_0(P5M1,n);BITN_1(P5M0,n); //////01 推挽输出 20mA 加限流
|
||||
|
#define D_HighR_P5(n) BITN_1(P5M1,n);BITN_0(P5M0,n); /////////10 高阻
|
||||
|
#define D_OpenD_P5(n) BITN_1(P5M1,n);BITN_1(P5M0,n); /////11 开漏 open-Drain 内部上拉电阻断开 开漏模式既可以度外部状态也可以对外输出高低电平
|
||||
|
|
||||
|
#define D_stdIO_P6(n) BITN_0(P6M1,n);BITN_0(P6M0,n); //////00 准双向口 灌电流20mA 拉电流270-150uS
|
||||
|
#define D_HighI_P6(n) BITN_0(P6M1,n);BITN_1(P6M0,n); //////01 推挽输出 20mA 加限流
|
||||
|
#define D_HighR_P6(n) BITN_1(P6M1,n);BITN_0(P6M0,n); /////////10 高阻
|
||||
|
#define D_OpenD_P6(n) BITN_1(P6M1,n);BITN_1(P6M0,n); /////11 开漏 open-Drain 内部上拉电阻断开 开漏模式既可以度外部状态也可以对外输出高低电平
|
||||
|
|
||||
|
#define D_stdIO_P7(n) BITN_0(P7M1,n);BITN_0(P7M0,n); //////00 准双向口 灌电流20mA 拉电流270-150uS
|
||||
|
#define D_HighI_P7(n) BITN_0(P7M1,n);BITN_1(P7M0,n); //////01 推挽输出 20mA 加限流
|
||||
|
#define D_HighR_P7(n) BITN_1(P7M1,n);BITN_0(P7M0,n); /////////10 高阻
|
||||
|
#define D_OpenD_P7(n) BITN_1(P7M1,n);BITN_1(P7M0,n); /////11 开漏 open-Drain 内部上拉电阻断开 开漏模式既可以度外部状态也可以对外输出高低电平
|
||||
|
|
||||
|
/***
|
||||
|
|
||||
|
#define P0_conf_in(n) BITN_1(P0M1,n);BITN_0(P0M0,n); |
||||
|
#define P1_conf_in(n) BITN_1(P1M1,n);BITN_0(P1M0,n); |
||||
|
#define P2_conf_in(n) BITN_1(P2M1,n);BITN_0(P2M0,n); |
||||
|
#define P2_conf_port(n) BITN_0(P2M1,n);BITN_0(P2M0,n); |
||||
|
|
||||
|
|
||||
|
#define P3_conf_in(n) BITN_1(P3M1,n);BITN_0(P3M0,n); |
||||
|
#define P3_conf_port(n) BITN_0(P3M1,n);BITN_0(P3M0,n); |
||||
|
|
||||
|
#define P4_conf_in(n) BITN_1(P4M1,n);BITN_0(P4M0,n); |
||||
|
#define P5_conf_in(n) BITN_1(P5M1,n);BITN_0(P5M0,n); |
||||
|
|
||||
|
***/ |
||||
|
|
||||
|
|
||||
|
|
||||
|
#define NOP() _nop_() |
||||
|
|
||||
|
#define L0_INT4_OPEN() BITN_1(INT_CLKO, INT_EX4) |
||||
|
#define L0_INT4_CLOSE() BITN_0(INT_CLKO, INT_EX4) |
||||
|
|
||||
|
#define L0_INT4_AT() BITN_G(INT_CLKO, INT_EX4) |
||||
|
|
||||
|
|
||||
|
|
||||
|
|
||||
|
#define L0_INT4_CLEAR() BITN_0(AUXINTIF, INT4IF) |
||||
|
#define L0_INT3_CLEAR() BITN_0(AUXINTIF, INT3IF) |
||||
|
#define L0_INT2_CLEAR() BITN_0(AUXINTIF, INT2IF) |
||||
|
|
||||
|
|
||||
|
|
||||
|
|
||||
|
//////
|
||||
|
|
||||
|
#define L0_INT3_OPEN() BITN_1(INT_CLKO, INT_EX3); |
||||
|
#define L0_INT3_CLOSE() BITN_0(INT_CLKO, INT_EX3); |
||||
|
#define L0_INT2_OPEN() BITN_1(INT_CLKO, INT_EX2); |
||||
|
#define L0_INT2_CLOSE() BITN_0(INT_CLKO, INT_EX2); |
||||
|
#define L0_INT1_OPEN() EX1 = 1; |
||||
|
#define L0_INT1_CLOSE() EX1 = 0; |
||||
|
#define L0_INT0_OPEN() EX0 = 1; |
||||
|
#define L0_INT0_CLOSE() EX0 = 0; |
||||
|
|
||||
|
#define D_ISR_int0 0 ///int0 下降沿触发 = 0 上下沿均可触发
|
||||
|
#define D_ISR_timer0 1 |
||||
|
#define D_ISR_int1 2 ///int1 下降沿触发 = 0 上下沿均可触发
|
||||
|
#define D_ISR_timer1 3 |
||||
|
#define D_ISR_int2 10 /////只有下降沿
|
||||
|
#define D_ISR_int3 11 /////只有下降沿
|
||||
|
#define D_SERVE_UART 4 |
||||
|
#define D_ISR_int4 16 /////只有下降沿
|
||||
|
|
||||
|
#if 0 |
||||
|
#define L0_TIMER1_start() TR1 = 1; |
||||
|
#define L0_TIMER1_end() TR1 = 0; |
||||
|
|
||||
|
|
||||
|
#define L0_TIMER1_isr_OPEN() ET1 = 1; |
||||
|
#define L0_TIMER1_isr_CLOSE() ET1 = 0; |
||||
|
|
||||
|
|
||||
|
#else |
||||
|
|
||||
|
#define L0_TIMER1_start() ET1 = 1; |
||||
|
#define L0_TIMER1_end() ET1 = 0; |
||||
|
|
||||
|
|
||||
|
#define L0_TIMER1_isr_OPEN() TR1 = 1; |
||||
|
#define L0_TIMER1_isr_CLOSE() TR1 = 0; |
||||
|
|
||||
|
|
||||
|
#endif |
||||
|
|
||||
|
/// fixme 颠倒定义会让c51锁死#define _nop_() NOP()
|
||||
|
|
||||
|
///#define L0_INT3_OPEN() BITN_1(INT_CLKO,INT_EX3); //使能INT3中断
|
||||
|
///#define L0_INT3_CLOSE() BITN_0(INT_CLKO,INT_EX3);
|
||||
|
#endif //STC_stc8a8k
|
||||
|
|
||||
|
|
||||
|
|
||||
|
|
||||
|
|
||||
|
|
@ -0,0 +1,640 @@ |
|||||
|
#ifndef __STC8H_H__ |
||||
|
#define __STC8H_H__ |
||||
|
|
||||
|
/////////////////////////////////////////////////
|
||||
|
|
||||
|
//包含本头文件后,不用另外再包含"REG51.H"
|
||||
|
|
||||
|
sfr P0 = 0x80; |
||||
|
sbit P00 = P0^0; |
||||
|
sbit P01 = P0^1; |
||||
|
sbit P02 = P0^2; |
||||
|
sbit P03 = P0^3; |
||||
|
sbit P04 = P0^4; |
||||
|
sbit P05 = P0^5; |
||||
|
sbit P06 = P0^6; |
||||
|
sbit P07 = P0^7; |
||||
|
sfr SP = 0x81; |
||||
|
sfr DPL = 0x82; |
||||
|
sfr DPH = 0x83; |
||||
|
sfr S4CON = 0x84; |
||||
|
sfr S4BUF = 0x85; |
||||
|
sfr PCON = 0x87; |
||||
|
sfr TCON = 0x88; |
||||
|
sbit TF1 = TCON^7; |
||||
|
sbit TR1 = TCON^6; |
||||
|
sbit TF0 = TCON^5; |
||||
|
sbit TR0 = TCON^4; |
||||
|
sbit IE1 = TCON^3; |
||||
|
sbit IT1 = TCON^2; |
||||
|
sbit IE0 = TCON^1; |
||||
|
sbit IT0 = TCON^0; |
||||
|
sfr TMOD = 0x89; |
||||
|
sfr TL0 = 0x8a; |
||||
|
sfr TL1 = 0x8b; |
||||
|
sfr TH0 = 0x8c; |
||||
|
sfr TH1 = 0x8d; |
||||
|
sfr AUXR = 0x8e; |
||||
|
sfr INTCLKO = 0x8f; |
||||
|
sfr P1 = 0x90; |
||||
|
sbit P10 = P1^0; |
||||
|
sbit P11 = P1^1; |
||||
|
sbit P12 = P1^2; |
||||
|
sbit P13 = P1^3; |
||||
|
sbit P14 = P1^4; |
||||
|
sbit P15 = P1^5; |
||||
|
sbit P16 = P1^6; |
||||
|
sbit P17 = P1^7; |
||||
|
sfr P1M1 = 0x91; |
||||
|
sfr P1M0 = 0x92; |
||||
|
sfr P0M1 = 0x93; |
||||
|
sfr P0M0 = 0x94; |
||||
|
sfr P2M1 = 0x95; |
||||
|
sfr P2M0 = 0x96; |
||||
|
sfr SCON = 0x98; |
||||
|
sbit SM0 = SCON^7; |
||||
|
sbit SM1 = SCON^6; |
||||
|
sbit SM2 = SCON^5; |
||||
|
sbit REN = SCON^4; |
||||
|
sbit TB8 = SCON^3; |
||||
|
sbit RB8 = SCON^2; |
||||
|
sbit TI = SCON^1; |
||||
|
sbit RI = SCON^0; |
||||
|
sfr SBUF = 0x99; |
||||
|
sfr S2CON = 0x9a; |
||||
|
sfr S2BUF = 0x9b; |
||||
|
sfr IRCBAND = 0x9d; |
||||
|
sfr LIRTRIM = 0x9e; |
||||
|
sfr IRTRIM = 0x9f; |
||||
|
sfr P2 = 0xa0; |
||||
|
sbit P20 = P2^0; |
||||
|
sbit P21 = P2^1; |
||||
|
sbit P22 = P2^2; |
||||
|
sbit P23 = P2^3; |
||||
|
sbit P24 = P2^4; |
||||
|
sbit P25 = P2^5; |
||||
|
sbit P26 = P2^6; |
||||
|
sbit P27 = P2^7; |
||||
|
sfr P_SW1 = 0xa2; |
||||
|
sfr IE = 0xa8; |
||||
|
sbit EA = IE^7; |
||||
|
sbit ELVD = IE^6; |
||||
|
sbit EADC = IE^5; |
||||
|
sbit ES = IE^4; |
||||
|
sbit ET1 = IE^3; |
||||
|
sbit EX1 = IE^2; |
||||
|
sbit ET0 = IE^1; |
||||
|
sbit EX0 = IE^0; |
||||
|
sfr SADDR = 0xa9; |
||||
|
sfr WKTCL = 0xaa; |
||||
|
sfr WKTCH = 0xab; |
||||
|
sfr S3CON = 0xac; |
||||
|
sfr S3BUF = 0xad; |
||||
|
sfr TA = 0xae; |
||||
|
sfr IE2 = 0xaf; |
||||
|
sfr P3 = 0xb0; |
||||
|
sbit P30 = P3^0; |
||||
|
sbit P31 = P3^1; |
||||
|
sbit P32 = P3^2; |
||||
|
sbit P33 = P3^3; |
||||
|
sbit P34 = P3^4; |
||||
|
sbit P35 = P3^5; |
||||
|
sbit P36 = P3^6; |
||||
|
sbit P37 = P3^7; |
||||
|
sfr P3M1 = 0xb1; |
||||
|
sfr P3M0 = 0xb2; |
||||
|
sfr P4M1 = 0xb3; |
||||
|
sfr P4M0 = 0xb4; |
||||
|
sfr IP2 = 0xb5; |
||||
|
sfr IP2H = 0xb6; |
||||
|
sfr IPH = 0xb7; |
||||
|
sfr IP = 0xb8; |
||||
|
sbit PPCA = IP^7; |
||||
|
sbit PLVD = IP^6; |
||||
|
sbit PADC = IP^5; |
||||
|
sbit PS = IP^4; |
||||
|
sbit PT1 = IP^3; |
||||
|
sbit PX1 = IP^2; |
||||
|
sbit PT0 = IP^1; |
||||
|
sbit PX0 = IP^0; |
||||
|
sfr SADEN = 0xb9; |
||||
|
sfr P_SW2 = 0xba; |
||||
|
sfr ADC_CONTR = 0xbc; |
||||
|
sfr ADC_RES = 0xbd; |
||||
|
sfr ADC_RESL = 0xbe; |
||||
|
sfr P4 = 0xc0; |
||||
|
sbit P40 = P4^0; |
||||
|
sbit P41 = P4^1; |
||||
|
sbit P42 = P4^2; |
||||
|
sbit P43 = P4^3; |
||||
|
sbit P44 = P4^4; |
||||
|
sbit P45 = P4^5; |
||||
|
sbit P46 = P4^6; |
||||
|
sbit P47 = P4^7; |
||||
|
sfr WDT_CONTR = 0xc1; |
||||
|
sfr IAP_DATA = 0xc2; |
||||
|
sfr IAP_ADDRH = 0xc3; |
||||
|
sfr IAP_ADDRL = 0xc4; |
||||
|
sfr IAP_CMD = 0xc5; |
||||
|
sfr IAP_TRIG = 0xc6; |
||||
|
sfr IAP_CONTR = 0xc7; |
||||
|
sfr P5 = 0xc8; |
||||
|
sbit P50 = P5^0; |
||||
|
sbit P51 = P5^1; |
||||
|
sbit P52 = P5^2; |
||||
|
sbit P53 = P5^3; |
||||
|
sbit P54 = P5^4; |
||||
|
sbit P55 = P5^5; |
||||
|
sbit P56 = P5^6; |
||||
|
sbit P57 = P5^7; |
||||
|
sfr P5M1 = 0xc9; |
||||
|
sfr P5M0 = 0xca; |
||||
|
sfr P6M1 = 0xcb; |
||||
|
sfr P6M0 = 0xcc; |
||||
|
sfr SPSTAT = 0xcd; |
||||
|
sfr SPCTL = 0xce; |
||||
|
sfr SPDAT = 0xcf; |
||||
|
sfr PSW = 0xd0; |
||||
|
sbit CY = PSW^7; |
||||
|
sbit AC = PSW^6; |
||||
|
sbit F0 = PSW^5; |
||||
|
sbit RS1 = PSW^4; |
||||
|
sbit RS0 = PSW^3; |
||||
|
sbit OV = PSW^2; |
||||
|
sbit F1 = PSW^1; |
||||
|
sbit P = PSW^0; |
||||
|
sfr T4T3M = 0xd1; |
||||
|
sfr T4H = 0xd2; |
||||
|
sfr T4L = 0xd3; |
||||
|
sfr T3H = 0xd4; |
||||
|
sfr T3L = 0xd5; |
||||
|
sfr T2H = 0xd6; |
||||
|
sfr T2L = 0xd7; |
||||
|
sfr USBCLK = 0xdc; |
||||
|
sfr ADCCFG = 0xde; |
||||
|
sfr IP3 = 0xdf; |
||||
|
sfr ACC = 0xe0; |
||||
|
sfr P7M1 = 0xe1; |
||||
|
sfr P7M0 = 0xe2; |
||||
|
sfr DPS = 0xe3; |
||||
|
sfr DPL1 = 0xe4; |
||||
|
sfr DPH1 = 0xe5; |
||||
|
sfr CMPCR1 = 0xe6; |
||||
|
sfr CMPCR2 = 0xe7; |
||||
|
sfr P6 = 0xe8; |
||||
|
sfr USBDAT = 0xec; |
||||
|
sfr IP3H = 0xee; |
||||
|
sfr AUXINTIF = 0xef; |
||||
|
sfr B = 0xf0; |
||||
|
sfr USBCON = 0xf4; |
||||
|
sfr IAP_TPS = 0xf5; |
||||
|
sfr P7 = 0xf8; |
||||
|
sfr USBADR = 0xfc; |
||||
|
sfr RSTCFG = 0xff; |
||||
|
|
||||
|
//如下特殊功能寄存器位于扩展RAM区域
|
||||
|
//访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写
|
||||
|
|
||||
|
/////////////////////////////////////////////////
|
||||
|
//FF00H-FFFFH
|
||||
|
/////////////////////////////////////////////////
|
||||
|
|
||||
|
|
||||
|
|
||||
|
/////////////////////////////////////////////////
|
||||
|
//FE00H-FEFFH
|
||||
|
/////////////////////////////////////////////////
|
||||
|
|
||||
|
#define CKSEL (*(unsigned char volatile xdata *)0xfe00) |
||||
|
#define CLKDIV (*(unsigned char volatile xdata *)0xfe01) |
||||
|
#define HIRCCR (*(unsigned char volatile xdata *)0xfe02) |
||||
|
#define XOSCCR (*(unsigned char volatile xdata *)0xfe03) |
||||
|
#define IRC32KCR (*(unsigned char volatile xdata *)0xfe04) |
||||
|
#define MCLKOCR (*(unsigned char volatile xdata *)0xfe05) |
||||
|
#define IRCDB (*(unsigned char volatile xdata *)0xfe06) |
||||
|
#define X32KCR (*(unsigned char volatile xdata *)0xfe08) |
||||
|
|
||||
|
#define P0PU (*(unsigned char volatile xdata *)0xfe10) |
||||
|
#define P1PU (*(unsigned char volatile xdata *)0xfe11) |
||||
|
#define P2PU (*(unsigned char volatile xdata *)0xfe12) |
||||
|
#define P3PU (*(unsigned char volatile xdata *)0xfe13) |
||||
|
#define P4PU (*(unsigned char volatile xdata *)0xfe14) |
||||
|
#define P5PU (*(unsigned char volatile xdata *)0xfe15) |
||||
|
#define P6PU (*(unsigned char volatile xdata *)0xfe16) |
||||
|
#define P7PU (*(unsigned char volatile xdata *)0xfe17) |
||||
|
#define P0NCS (*(unsigned char volatile xdata *)0xfe18) |
||||
|
#define P1NCS (*(unsigned char volatile xdata *)0xfe19) |
||||
|
#define P2NCS (*(unsigned char volatile xdata *)0xfe1a) |
||||
|
#define P3NCS (*(unsigned char volatile xdata *)0xfe1b) |
||||
|
#define P4NCS (*(unsigned char volatile xdata *)0xfe1c) |
||||
|
#define P5NCS (*(unsigned char volatile xdata *)0xfe1d) |
||||
|
#define P6NCS (*(unsigned char volatile xdata *)0xfe1e) |
||||
|
#define P7NCS (*(unsigned char volatile xdata *)0xfe1f) |
||||
|
#define P0SR (*(unsigned char volatile xdata *)0xfe20) |
||||
|
#define P1SR (*(unsigned char volatile xdata *)0xfe21) |
||||
|
#define P2SR (*(unsigned char volatile xdata *)0xfe22) |
||||
|
#define P3SR (*(unsigned char volatile xdata *)0xfe23) |
||||
|
#define P4SR (*(unsigned char volatile xdata *)0xfe24) |
||||
|
#define P5SR (*(unsigned char volatile xdata *)0xfe25) |
||||
|
#define P6SR (*(unsigned char volatile xdata *)0xfe26) |
||||
|
#define P7SR (*(unsigned char volatile xdata *)0xfe27) |
||||
|
#define P0DR (*(unsigned char volatile xdata *)0xfe28) |
||||
|
#define P1DR (*(unsigned char volatile xdata *)0xfe29) |
||||
|
#define P2DR (*(unsigned char volatile xdata *)0xfe2a) |
||||
|
#define P3DR (*(unsigned char volatile xdata *)0xfe2b) |
||||
|
#define P4DR (*(unsigned char volatile xdata *)0xfe2c) |
||||
|
#define P5DR (*(unsigned char volatile xdata *)0xfe2d) |
||||
|
#define P6DR (*(unsigned char volatile xdata *)0xfe2e) |
||||
|
#define P7DR (*(unsigned char volatile xdata *)0xfe2f) |
||||
|
#define P0IE (*(unsigned char volatile xdata *)0xfe30) |
||||
|
#define P1IE (*(unsigned char volatile xdata *)0xfe31) |
||||
|
#define P2IE (*(unsigned char volatile xdata *)0xfe32) |
||||
|
#define P3IE (*(unsigned char volatile xdata *)0xfe33) |
||||
|
#define P4IE (*(unsigned char volatile xdata *)0xfe34) |
||||
|
#define P5IE (*(unsigned char volatile xdata *)0xfe35) |
||||
|
#define P6IE (*(unsigned char volatile xdata *)0xfe36) |
||||
|
#define P7IE (*(unsigned char volatile xdata *)0xfe37) |
||||
|
|
||||
|
#define RTCCR (*(unsigned char volatile xdata *)0xfe60) |
||||
|
#define RTCCFG (*(unsigned char volatile xdata *)0xfe61) |
||||
|
#define RTCIEN (*(unsigned char volatile xdata *)0xfe62) |
||||
|
#define RTCIF (*(unsigned char volatile xdata *)0xfe63) |
||||
|
#define ALAHOUR (*(unsigned char volatile xdata *)0xfe64) |
||||
|
#define ALAMIN (*(unsigned char volatile xdata *)0xfe65) |
||||
|
#define ALASEC (*(unsigned char volatile xdata *)0xfe66) |
||||
|
#define ALASSEC (*(unsigned char volatile xdata *)0xfe67) |
||||
|
#define INIYEAR (*(unsigned char volatile xdata *)0xfe68) |
||||
|
#define INIMONTH (*(unsigned char volatile xdata *)0xfe69) |
||||
|
#define INIDAY (*(unsigned char volatile xdata *)0xfe6a) |
||||
|
#define INIHOUR (*(unsigned char volatile xdata *)0xfe6b) |
||||
|
#define INIMIN (*(unsigned char volatile xdata *)0xfe6c) |
||||
|
#define INISEC (*(unsigned char volatile xdata *)0xfe6d) |
||||
|
#define INISSEC (*(unsigned char volatile xdata *)0xfe6e) |
||||
|
#define YEAR (*(unsigned char volatile xdata *)0xfe70) |
||||
|
#define MONTH (*(unsigned char volatile xdata *)0xfe71) |
||||
|
#define DAY (*(unsigned char volatile xdata *)0xfe72) |
||||
|
#define HOUR (*(unsigned char volatile xdata *)0xfe73) |
||||
|
#define MIN (*(unsigned char volatile xdata *)0xfe74) |
||||
|
#define SEC (*(unsigned char volatile xdata *)0xfe75) |
||||
|
#define SSEC (*(unsigned char volatile xdata *)0xfe76) |
||||
|
|
||||
|
#define I2CCFG (*(unsigned char volatile xdata *)0xfe80) |
||||
|
#define I2CMSCR (*(unsigned char volatile xdata *)0xfe81) |
||||
|
#define I2CMSST (*(unsigned char volatile xdata *)0xfe82) |
||||
|
#define I2CSLCR (*(unsigned char volatile xdata *)0xfe83) |
||||
|
#define I2CSLST (*(unsigned char volatile xdata *)0xfe84) |
||||
|
#define I2CSLADR (*(unsigned char volatile xdata *)0xfe85) |
||||
|
#define I2CTXD (*(unsigned char volatile xdata *)0xfe86) |
||||
|
#define I2CRXD (*(unsigned char volatile xdata *)0xfe87) |
||||
|
#define I2CMSAUX (*(unsigned char volatile xdata *)0xfe88) |
||||
|
#define TM2PS (*(unsigned char volatile xdata *)0xfea2) |
||||
|
#define TM3PS (*(unsigned char volatile xdata *)0xfea3) |
||||
|
#define TM4PS (*(unsigned char volatile xdata *)0xfea4) |
||||
|
#define ADCTIM (*(unsigned char volatile xdata *)0xfea8) |
||||
|
|
||||
|
#define PWM1_ETRPS (*(unsigned char volatile xdata *)0xfeb0) |
||||
|
#define PWM1_ENO (*(unsigned char volatile xdata *)0xfeb1) |
||||
|
#define PWM1_PS (*(unsigned char volatile xdata *)0xfeb2) |
||||
|
#define PWM1_IOAUX (*(unsigned char volatile xdata *)0xfeb3) |
||||
|
#define PWM2_ETRPS (*(unsigned char volatile xdata *)0xfeb4) |
||||
|
#define PWM2_ENO (*(unsigned char volatile xdata *)0xfeb5) |
||||
|
#define PWM2_PS (*(unsigned char volatile xdata *)0xfeb6) |
||||
|
#define PWM2_IOAUX (*(unsigned char volatile xdata *)0xfeb7) |
||||
|
#define PWM1_CR1 (*(unsigned char volatile xdata *)0xfec0) |
||||
|
#define PWM1_CR2 (*(unsigned char volatile xdata *)0xfec1) |
||||
|
#define PWM1_SMCR (*(unsigned char volatile xdata *)0xfec2) |
||||
|
#define PWM1_ETR (*(unsigned char volatile xdata *)0xfec3) |
||||
|
#define PWM1_IER (*(unsigned char volatile xdata *)0xfec4) |
||||
|
#define PWM1_SR1 (*(unsigned char volatile xdata *)0xfec5) |
||||
|
#define PWM1_SR2 (*(unsigned char volatile xdata *)0xfec6) |
||||
|
#define PWM1_EGR (*(unsigned char volatile xdata *)0xfec7) |
||||
|
#define PWM1_CCMR1 (*(unsigned char volatile xdata *)0xfec8) |
||||
|
#define PWM1_CCMR2 (*(unsigned char volatile xdata *)0xfec9) |
||||
|
#define PWM1_CCMR3 (*(unsigned char volatile xdata *)0xfeca) |
||||
|
#define PWM1_CCMR4 (*(unsigned char volatile xdata *)0xfecb) |
||||
|
#define PWM1_CCER1 (*(unsigned char volatile xdata *)0xfecc) |
||||
|
#define PWM1_CCER2 (*(unsigned char volatile xdata *)0xfecd) |
||||
|
#define PWM1_CNTR (*(unsigned int volatile xdata *)0xfece) |
||||
|
#define PWM1_CNTRH (*(unsigned char volatile xdata *)0xfece) |
||||
|
#define PWM1_CNTRL (*(unsigned char volatile xdata *)0xfecf) |
||||
|
#define PWM1_PSCR (*(unsigned int volatile xdata *)0xfed0) |
||||
|
#define PWM1_PSCRH (*(unsigned char volatile xdata *)0xfed0) |
||||
|
#define PWM1_PSCRL (*(unsigned char volatile xdata *)0xfed1) |
||||
|
#define PWM1_ARR (*(unsigned int volatile xdata *)0xfed2) |
||||
|
#define PWM1_ARRH (*(unsigned char volatile xdata *)0xfed2) |
||||
|
#define PWM1_ARRL (*(unsigned char volatile xdata *)0xfed3) |
||||
|
#define PWM1_RCR (*(unsigned char volatile xdata *)0xfed4) |
||||
|
#define PWM1_CCR1 (*(unsigned int volatile xdata *)0xfed5) |
||||
|
#define PWM1_CCR1H (*(unsigned char volatile xdata *)0xfed5) |
||||
|
#define PWM1_CCR1L (*(unsigned char volatile xdata *)0xfed6) |
||||
|
#define PWM1_CCR2 (*(unsigned int volatile xdata *)0xfed7) |
||||
|
#define PWM1_CCR2H (*(unsigned char volatile xdata *)0xfed7) |
||||
|
#define PWM1_CCR2L (*(unsigned char volatile xdata *)0xfed8) |
||||
|
#define PWM1_CCR3 (*(unsigned int volatile xdata *)0xfed9) |
||||
|
#define PWM1_CCR3H (*(unsigned char volatile xdata *)0xfed9) |
||||
|
#define PWM1_CCR3L (*(unsigned char volatile xdata *)0xfeda) |
||||
|
#define PWM1_CCR4 (*(unsigned int volatile xdata *)0xfedb) |
||||
|
#define PWM1_CCR4H (*(unsigned char volatile xdata *)0xfedb) |
||||
|
#define PWM1_CCR4L (*(unsigned char volatile xdata *)0xfedc) |
||||
|
#define PWM1_BKR (*(unsigned char volatile xdata *)0xfedd) |
||||
|
#define PWM1_DTR (*(unsigned char volatile xdata *)0xfede) |
||||
|
#define PWM1_OISR (*(unsigned char volatile xdata *)0xfedf) |
||||
|
#define PWM2_CR1 (*(unsigned char volatile xdata *)0xfee0) |
||||
|
#define PWM2_CR2 (*(unsigned char volatile xdata *)0xfee1) |
||||
|
#define PWM2_SMCR (*(unsigned char volatile xdata *)0xfee2) |
||||
|
#define PWM2_ETR (*(unsigned char volatile xdata *)0xfee3) |
||||
|
#define PWM2_IER (*(unsigned char volatile xdata *)0xfee4) |
||||
|
#define PWM2_SR1 (*(unsigned char volatile xdata *)0xfee5) |
||||
|
#define PWM2_SR2 (*(unsigned char volatile xdata *)0xfee6) |
||||
|
#define PWM2_EGR (*(unsigned char volatile xdata *)0xfee7) |
||||
|
#define PWM2_CCMR1 (*(unsigned char volatile xdata *)0xfee8) |
||||
|
#define PWM2_CCMR2 (*(unsigned char volatile xdata *)0xfee9) |
||||
|
#define PWM2_CCMR3 (*(unsigned char volatile xdata *)0xfeea) |
||||
|
#define PWM2_CCMR4 (*(unsigned char volatile xdata *)0xfeeb) |
||||
|
#define PWM2_CCER1 (*(unsigned char volatile xdata *)0xfeec) |
||||
|
#define PWM2_CCER2 (*(unsigned char volatile xdata *)0xfeed) |
||||
|
#define PWM2_CNTR (*(unsigned int volatile xdata *)0xfeee) |
||||
|
#define PWM2_CNTRH (*(unsigned char volatile xdata *)0xfeee) |
||||
|
#define PWM2_CNTRL (*(unsigned char volatile xdata *)0xfeef) |
||||
|
#define PWM2_PSCR (*(unsigned int volatile xdata *)0xfef0) |
||||
|
#define PWM2_PSCRH (*(unsigned char volatile xdata *)0xfef0) |
||||
|
#define PWM2_PSCRL (*(unsigned char volatile xdata *)0xfef1) |
||||
|
#define PWM2_ARR (*(unsigned int volatile xdata *)0xfef2) |
||||
|
#define PWM2_ARRH (*(unsigned char volatile xdata *)0xfef2) |
||||
|
#define PWM2_ARRL (*(unsigned char volatile xdata *)0xfef3) |
||||
|
#define PWM2_RCR (*(unsigned char volatile xdata *)0xfef4) |
||||
|
#define PWM2_CCR1 (*(unsigned int volatile xdata *)0xfef5) |
||||
|
#define PWM2_CCR1H (*(unsigned char volatile xdata *)0xfef5) |
||||
|
#define PWM2_CCR1L (*(unsigned char volatile xdata *)0xfef6) |
||||
|
#define PWM2_CCR2 (*(unsigned int volatile xdata *)0xfef7) |
||||
|
#define PWM2_CCR2H (*(unsigned char volatile xdata *)0xfef7) |
||||
|
#define PWM2_CCR2L (*(unsigned char volatile xdata *)0xfef8) |
||||
|
#define PWM2_CCR3 (*(unsigned int volatile xdata *)0xfef9) |
||||
|
#define PWM2_CCR3H (*(unsigned char volatile xdata *)0xfef9) |
||||
|
#define PWM2_CCR3L (*(unsigned char volatile xdata *)0xfefa) |
||||
|
#define PWM2_CCR4 (*(unsigned int volatile xdata *)0xfefb) |
||||
|
#define PWM2_CCR4H (*(unsigned char volatile xdata *)0xfefb) |
||||
|
#define PWM2_CCR4L (*(unsigned char volatile xdata *)0xfefc) |
||||
|
#define PWM2_BKR (*(unsigned char volatile xdata *)0xfefd) |
||||
|
#define PWM2_DTR (*(unsigned char volatile xdata *)0xfefe) |
||||
|
#define PWM2_OISR (*(unsigned char volatile xdata *)0xfeff) |
||||
|
|
||||
|
#define PWMA_ETRPS (*(unsigned char volatile xdata *)0xfeb0) |
||||
|
#define PWMA_ENO (*(unsigned char volatile xdata *)0xfeb1) |
||||
|
#define PWMA_PS (*(unsigned char volatile xdata *)0xfeb2) |
||||
|
#define PWMA_IOAUX (*(unsigned char volatile xdata *)0xfeb3) |
||||
|
#define PWMB_ETRPS (*(unsigned char volatile xdata *)0xfeb4) |
||||
|
#define PWMB_ENO (*(unsigned char volatile xdata *)0xfeb5) |
||||
|
#define PWMB_PS (*(unsigned char volatile xdata *)0xfeb6) |
||||
|
#define PWMB_IOAUX (*(unsigned char volatile xdata *)0xfeb7) |
||||
|
#define PWMA_CR1 (*(unsigned char volatile xdata *)0xfec0) |
||||
|
#define PWMA_CR2 (*(unsigned char volatile xdata *)0xfec1) |
||||
|
#define PWMA_SMCR (*(unsigned char volatile xdata *)0xfec2) |
||||
|
#define PWMA_ETR (*(unsigned char volatile xdata *)0xfec3) |
||||
|
#define PWMA_IER (*(unsigned char volatile xdata *)0xfec4) |
||||
|
#define PWMA_SR1 (*(unsigned char volatile xdata *)0xfec5) |
||||
|
#define PWMA_SR2 (*(unsigned char volatile xdata *)0xfec6) |
||||
|
#define PWMA_EGR (*(unsigned char volatile xdata *)0xfec7) |
||||
|
#define PWMA_CCMR1 (*(unsigned char volatile xdata *)0xfec8) |
||||
|
#define PWMA_CCMR2 (*(unsigned char volatile xdata *)0xfec9) |
||||
|
#define PWMA_CCMR3 (*(unsigned char volatile xdata *)0xfeca) |
||||
|
#define PWMA_CCMR4 (*(unsigned char volatile xdata *)0xfecb) |
||||
|
#define PWMA_CCER1 (*(unsigned char volatile xdata *)0xfecc) |
||||
|
#define PWMA_CCER2 (*(unsigned char volatile xdata *)0xfecd) |
||||
|
#define PWMA_CNTR (*(unsigned int volatile xdata *)0xfece) |
||||
|
#define PWMA_CNTRH (*(unsigned char volatile xdata *)0xfece) |
||||
|
#define PWMA_CNTRL (*(unsigned char volatile xdata *)0xfecf) |
||||
|
#define PWMA_PSCR (*(unsigned int volatile xdata *)0xfed0) |
||||
|
#define PWMA_PSCRH (*(unsigned char volatile xdata *)0xfed0) |
||||
|
#define PWMA_PSCRL (*(unsigned char volatile xdata *)0xfed1) |
||||
|
#define PWMA_ARR (*(unsigned int volatile xdata *)0xfed2) |
||||
|
#define PWMA_ARRH (*(unsigned char volatile xdata *)0xfed2) |
||||
|
#define PWMA_ARRL (*(unsigned char volatile xdata *)0xfed3) |
||||
|
#define PWMA_RCR (*(unsigned char volatile xdata *)0xfed4) |
||||
|
#define PWMA_CCR1 (*(unsigned int volatile xdata *)0xfed5) |
||||
|
#define PWMA_CCR1H (*(unsigned char volatile xdata *)0xfed5) |
||||
|
#define PWMA_CCR1L (*(unsigned char volatile xdata *)0xfed6) |
||||
|
#define PWMA_CCR2 (*(unsigned int volatile xdata *)0xfed7) |
||||
|
#define PWMA_CCR2H (*(unsigned char volatile xdata *)0xfed7) |
||||
|
#define PWMA_CCR2L (*(unsigned char volatile xdata *)0xfed8) |
||||
|
#define PWMA_CCR3 (*(unsigned int volatile xdata *)0xfed9) |
||||
|
#define PWMA_CCR3H (*(unsigned char volatile xdata *)0xfed9) |
||||
|
#define PWMA_CCR3L (*(unsigned char volatile xdata *)0xfeda) |
||||
|
#define PWMA_CCR4 (*(unsigned int volatile xdata *)0xfedb) |
||||
|
#define PWMA_CCR4H (*(unsigned char volatile xdata *)0xfedb) |
||||
|
#define PWMA_CCR4L (*(unsigned char volatile xdata *)0xfedc) |
||||
|
#define PWMA_BKR (*(unsigned char volatile xdata *)0xfedd) |
||||
|
#define PWMA_DTR (*(unsigned char volatile xdata *)0xfede) |
||||
|
#define PWMA_OISR (*(unsigned char volatile xdata *)0xfedf) |
||||
|
#define PWMB_CR1 (*(unsigned char volatile xdata *)0xfee0) |
||||
|
#define PWMB_CR2 (*(unsigned char volatile xdata *)0xfee1) |
||||
|
#define PWMB_SMCR (*(unsigned char volatile xdata *)0xfee2) |
||||
|
#define PWMB_ETR (*(unsigned char volatile xdata *)0xfee3) |
||||
|
#define PWMB_IER (*(unsigned char volatile xdata *)0xfee4) |
||||
|
#define PWMB_SR1 (*(unsigned char volatile xdata *)0xfee5) |
||||
|
#define PWMB_SR2 (*(unsigned char volatile xdata *)0xfee6) |
||||
|
#define PWMB_EGR (*(unsigned char volatile xdata *)0xfee7) |
||||
|
#define PWMB_CCMR1 (*(unsigned char volatile xdata *)0xfee8) |
||||
|
#define PWMB_CCMR2 (*(unsigned char volatile xdata *)0xfee9) |
||||
|
#define PWMB_CCMR3 (*(unsigned char volatile xdata *)0xfeea) |
||||
|
#define PWMB_CCMR4 (*(unsigned char volatile xdata *)0xfeeb) |
||||
|
#define PWMB_CCER1 (*(unsigned char volatile xdata *)0xfeec) |
||||
|
#define PWMB_CCER2 (*(unsigned char volatile xdata *)0xfeed) |
||||
|
#define PWMB_CNTR (*(unsigned int volatile xdata *)0xfeee) |
||||
|
#define PWMB_CNTRH (*(unsigned char volatile xdata *)0xfeee) |
||||
|
#define PWMB_CNTRL (*(unsigned char volatile xdata *)0xfeef) |
||||
|
#define PWMB_PSCR (*(unsigned int volatile xdata *)0xfef0) |
||||
|
#define PWMB_PSCRH (*(unsigned char volatile xdata *)0xfef0) |
||||
|
#define PWMB_PSCRL (*(unsigned char volatile xdata *)0xfef1) |
||||
|
#define PWMB_ARR (*(unsigned int volatile xdata *)0xfef2) |
||||
|
#define PWMB_ARRH (*(unsigned char volatile xdata *)0xfef2) |
||||
|
#define PWMB_ARRL (*(unsigned char volatile xdata *)0xfef3) |
||||
|
#define PWMB_RCR (*(unsigned char volatile xdata *)0xfef4) |
||||
|
#define PWMB_CCR5 (*(unsigned int volatile xdata *)0xfef5) |
||||
|
#define PWMB_CCR5H (*(unsigned char volatile xdata *)0xfef5) |
||||
|
#define PWMB_CCR5L (*(unsigned char volatile xdata *)0xfef6) |
||||
|
#define PWMB_CCR6 (*(unsigned int volatile xdata *)0xfef7) |
||||
|
#define PWMB_CCR6H (*(unsigned char volatile xdata *)0xfef7) |
||||
|
#define PWMB_CCR6L (*(unsigned char volatile xdata *)0xfef8) |
||||
|
#define PWMB_CCR7 (*(unsigned int volatile xdata *)0xfef9) |
||||
|
#define PWMB_CCR7H (*(unsigned char volatile xdata *)0xfef9) |
||||
|
#define PWMB_CCR7L (*(unsigned char volatile xdata *)0xfefa) |
||||
|
#define PWMB_CCR8 (*(unsigned int volatile xdata *)0xfefb) |
||||
|
#define PWMB_CCR8H (*(unsigned char volatile xdata *)0xfefb) |
||||
|
#define PWMB_CCR8L (*(unsigned char volatile xdata *)0xfefc) |
||||
|
#define PWMB_BKR (*(unsigned char volatile xdata *)0xfefd) |
||||
|
#define PWMB_DTR (*(unsigned char volatile xdata *)0xfefe) |
||||
|
#define PWMB_OISR (*(unsigned char volatile xdata *)0xfeff) |
||||
|
|
||||
|
/////////////////////////////////////////////////
|
||||
|
//FD00H-FDFFH
|
||||
|
/////////////////////////////////////////////////
|
||||
|
|
||||
|
#define P0INTE (*(unsigned char volatile xdata *)0xfd00) |
||||
|
#define P1INTE (*(unsigned char volatile xdata *)0xfd01) |
||||
|
#define P2INTE (*(unsigned char volatile xdata *)0xfd02) |
||||
|
#define P3INTE (*(unsigned char volatile xdata *)0xfd03) |
||||
|
#define P4INTE (*(unsigned char volatile xdata *)0xfd04) |
||||
|
#define P5INTE (*(unsigned char volatile xdata *)0xfd05) |
||||
|
#define P6INTE (*(unsigned char volatile xdata *)0xfd06) |
||||
|
#define P7INTE (*(unsigned char volatile xdata *)0xfd07) |
||||
|
#define P0INTF (*(unsigned char volatile xdata *)0xfd10) |
||||
|
#define P1INTF (*(unsigned char volatile xdata *)0xfd11) |
||||
|
#define P2INTF (*(unsigned char volatile xdata *)0xfd12) |
||||
|
#define P3INTF (*(unsigned char volatile xdata *)0xfd13) |
||||
|
#define P4INTF (*(unsigned char volatile xdata *)0xfd14) |
||||
|
#define P5INTF (*(unsigned char volatile xdata *)0xfd15) |
||||
|
#define P6INTF (*(unsigned char volatile xdata *)0xfd16) |
||||
|
#define P7INTF (*(unsigned char volatile xdata *)0xfd17) |
||||
|
#define P0IM0 (*(unsigned char volatile xdata *)0xfd20) |
||||
|
#define P1IM0 (*(unsigned char volatile xdata *)0xfd21) |
||||
|
#define P2IM0 (*(unsigned char volatile xdata *)0xfd22) |
||||
|
#define P3IM0 (*(unsigned char volatile xdata *)0xfd23) |
||||
|
#define P4IM0 (*(unsigned char volatile xdata *)0xfd24) |
||||
|
#define P5IM0 (*(unsigned char volatile xdata *)0xfd25) |
||||
|
#define P6IM0 (*(unsigned char volatile xdata *)0xfd26) |
||||
|
#define P7IM0 (*(unsigned char volatile xdata *)0xfd27) |
||||
|
#define P0IM1 (*(unsigned char volatile xdata *)0xfd30) |
||||
|
#define P1IM1 (*(unsigned char volatile xdata *)0xfd31) |
||||
|
#define P2IM1 (*(unsigned char volatile xdata *)0xfd32) |
||||
|
#define P3IM1 (*(unsigned char volatile xdata *)0xfd33) |
||||
|
#define P4IM1 (*(unsigned char volatile xdata *)0xfd34) |
||||
|
#define P5IM1 (*(unsigned char volatile xdata *)0xfd35) |
||||
|
#define P6IM1 (*(unsigned char volatile xdata *)0xfd36) |
||||
|
#define P7IM1 (*(unsigned char volatile xdata *)0xfd37) |
||||
|
#define P0WKUE (*(unsigned char volatile xdata *)0xfd40) |
||||
|
#define P1WKUE (*(unsigned char volatile xdata *)0xfd41) |
||||
|
#define P2WKUE (*(unsigned char volatile xdata *)0xfd42) |
||||
|
#define P3WKUE (*(unsigned char volatile xdata *)0xfd43) |
||||
|
#define P4WKUE (*(unsigned char volatile xdata *)0xfd44) |
||||
|
#define P5WKUE (*(unsigned char volatile xdata *)0xfd45) |
||||
|
#define P6WKUE (*(unsigned char volatile xdata *)0xfd46) |
||||
|
#define P7WKUE (*(unsigned char volatile xdata *)0xfd47) |
||||
|
#define PIN_IP (*(unsigned char volatile xdata *)0xfd60) |
||||
|
#define PIN_IPH (*(unsigned char volatile xdata *)0xfd61) |
||||
|
|
||||
|
/////////////////////////////////////////////////
|
||||
|
//FC00H-FCFFH
|
||||
|
/////////////////////////////////////////////////
|
||||
|
|
||||
|
#define MD3 (*(unsigned char volatile xdata *)0xfcf0) |
||||
|
#define MD2 (*(unsigned char volatile xdata *)0xfcf1) |
||||
|
#define MD1 (*(unsigned char volatile xdata *)0xfcf2) |
||||
|
#define MD0 (*(unsigned char volatile xdata *)0xfcf3) |
||||
|
#define MD5 (*(unsigned char volatile xdata *)0xfcf4) |
||||
|
#define MD4 (*(unsigned char volatile xdata *)0xfcf5) |
||||
|
#define ARCON (*(unsigned char volatile xdata *)0xfcf6) |
||||
|
#define OPCON (*(unsigned char volatile xdata *)0xfcf7) |
||||
|
|
||||
|
/////////////////////////////////////////////////
|
||||
|
//FB00H-FBFFH
|
||||
|
/////////////////////////////////////////////////
|
||||
|
|
||||
|
#define COMEN (*(unsigned char volatile xdata *)0xfb00) |
||||
|
#define SEGENL (*(unsigned char volatile xdata *)0xfb01) |
||||
|
#define SEGENH (*(unsigned char volatile xdata *)0xfb02) |
||||
|
#define LEDCTRL (*(unsigned char volatile xdata *)0xfb03) |
||||
|
#define LEDCKS (*(unsigned char volatile xdata *)0xfb04) |
||||
|
#define COM0_DA_L (*(unsigned char volatile xdata *)0xfb10) |
||||
|
#define COM1_DA_L (*(unsigned char volatile xdata *)0xfb11) |
||||
|
#define COM2_DA_L (*(unsigned char volatile xdata *)0xfb12) |
||||
|
#define COM3_DA_L (*(unsigned char volatile xdata *)0xfb13) |
||||
|
#define COM4_DA_L (*(unsigned char volatile xdata *)0xfb14) |
||||
|
#define COM5_DA_L (*(unsigned char volatile xdata *)0xfb15) |
||||
|
#define COM6_DA_L (*(unsigned char volatile xdata *)0xfb16) |
||||
|
#define COM7_DA_L (*(unsigned char volatile xdata *)0xfb17) |
||||
|
#define COM0_DA_H (*(unsigned char volatile xdata *)0xfb18) |
||||
|
#define COM1_DA_H (*(unsigned char volatile xdata *)0xfb19) |
||||
|
#define COM2_DA_H (*(unsigned char volatile xdata *)0xfb1a) |
||||
|
#define COM3_DA_H (*(unsigned char volatile xdata *)0xfb1b) |
||||
|
#define COM4_DA_H (*(unsigned char volatile xdata *)0xfb1c) |
||||
|
#define COM5_DA_H (*(unsigned char volatile xdata *)0xfb1d) |
||||
|
#define COM6_DA_H (*(unsigned char volatile xdata *)0xfb1e) |
||||
|
#define COM7_DA_H (*(unsigned char volatile xdata *)0xfb1f) |
||||
|
#define COM0_DC_L (*(unsigned char volatile xdata *)0xfb20) |
||||
|
#define COM1_DC_L (*(unsigned char volatile xdata *)0xfb21) |
||||
|
#define COM2_DC_L (*(unsigned char volatile xdata *)0xfb22) |
||||
|
#define COM3_DC_L (*(unsigned char volatile xdata *)0xfb23) |
||||
|
#define COM4_DC_L (*(unsigned char volatile xdata *)0xfb24) |
||||
|
#define COM5_DC_L (*(unsigned char volatile xdata *)0xfb25) |
||||
|
#define COM6_DC_L (*(unsigned char volatile xdata *)0xfb26) |
||||
|
#define COM7_DC_L (*(unsigned char volatile xdata *)0xfb27) |
||||
|
#define COM0_DC_H (*(unsigned char volatile xdata *)0xfb28) |
||||
|
#define COM1_DC_H (*(unsigned char volatile xdata *)0xfb29) |
||||
|
#define COM2_DC_H (*(unsigned char volatile xdata *)0xfb2a) |
||||
|
#define COM3_DC_H (*(unsigned char volatile xdata *)0xfb2b) |
||||
|
#define COM4_DC_H (*(unsigned char volatile xdata *)0xfb2c) |
||||
|
#define COM5_DC_H (*(unsigned char volatile xdata *)0xfb2d) |
||||
|
#define COM6_DC_H (*(unsigned char volatile xdata *)0xfb2e) |
||||
|
#define COM7_DC_H (*(unsigned char volatile xdata *)0xfb2f) |
||||
|
|
||||
|
#define TSCHEN1 (*(unsigned char volatile xdata *)0xfb40) |
||||
|
#define TSCHEN2 (*(unsigned char volatile xdata *)0xfb41) |
||||
|
#define TSCFG1 (*(unsigned char volatile xdata *)0xfb42) |
||||
|
#define TSCFG2 (*(unsigned char volatile xdata *)0xfb43) |
||||
|
#define TSWUTC (*(unsigned char volatile xdata *)0xfb44) |
||||
|
#define TSCTRL (*(unsigned char volatile xdata *)0xfb45) |
||||
|
#define TSSTA1 (*(unsigned char volatile xdata *)0xfb46) |
||||
|
#define TSSTA2 (*(unsigned char volatile xdata *)0xfb47) |
||||
|
#define TSRT (*(unsigned char volatile xdata *)0xfb48) |
||||
|
#define TSDAT (*(unsigned int volatile xdata *)0xfb49) |
||||
|
#define TSDATH (*(unsigned char volatile xdata *)0xfb49) |
||||
|
#define TSDATL (*(unsigned char volatile xdata *)0xfb4A) |
||||
|
#define TSTH00 (*(unsigned int volatile xdata *)0xfb50) |
||||
|
#define TSTH00H (*(unsigned char volatile xdata *)0xfb50) |
||||
|
#define TSTH00L (*(unsigned char volatile xdata *)0xfb51) |
||||
|
#define TSTH01 (*(unsigned int volatile xdata *)0xfb52) |
||||
|
#define TSTH01H (*(unsigned char volatile xdata *)0xfb52) |
||||
|
#define TSTH01L (*(unsigned char volatile xdata *)0xfb53) |
||||
|
#define TSTH02 (*(unsigned int volatile xdata *)0xfb54) |
||||
|
#define TSTH02H (*(unsigned char volatile xdata *)0xfb54) |
||||
|
#define TSTH02L (*(unsigned char volatile xdata *)0xfb55) |
||||
|
#define TSTH03 (*(unsigned int volatile xdata *)0xfb56) |
||||
|
#define TSTH03H (*(unsigned char volatile xdata *)0xfb56) |
||||
|
#define TSTH03L (*(unsigned char volatile xdata *)0xfb57) |
||||
|
#define TSTH04 (*(unsigned int volatile xdata *)0xfb58) |
||||
|
#define TSTH04H (*(unsigned char volatile xdata *)0xfb58) |
||||
|
#define TSTH04L (*(unsigned char volatile xdata *)0xfb59) |
||||
|
#define TSTH05 (*(unsigned int volatile xdata *)0xfb5a) |
||||
|
#define TSTH05H (*(unsigned char volatile xdata *)0xfb5a) |
||||
|
#define TSTH05L (*(unsigned char volatile xdata *)0xfb5b) |
||||
|
#define TSTH06 (*(unsigned int volatile xdata *)0xfb5c) |
||||
|
#define TSTH06H (*(unsigned char volatile xdata *)0xfb5c) |
||||
|
#define TSTH06L (*(unsigned char volatile xdata *)0xfb5d) |
||||
|
#define TSTH07 (*(unsigned int volatile xdata *)0xfb5e) |
||||
|
#define TSTH07H (*(unsigned char volatile xdata *)0xfb5e) |
||||
|
#define TSTH07L (*(unsigned char volatile xdata *)0xfb5f) |
||||
|
#define TSTH08 (*(unsigned int volatile xdata *)0xfb60) |
||||
|
#define TSTH08H (*(unsigned char volatile xdata *)0xfb60) |
||||
|
#define TSTH08L (*(unsigned char volatile xdata *)0xfb61) |
||||
|
#define TSTH09 (*(unsigned int volatile xdata *)0xfb62) |
||||
|
#define TSTH09H (*(unsigned char volatile xdata *)0xfb62) |
||||
|
#define TSTH09L (*(unsigned char volatile xdata *)0xfb63) |
||||
|
#define TSTH10 (*(unsigned int volatile xdata *)0xfb64) |
||||
|
#define TSTH10H (*(unsigned char volatile xdata *)0xfb64) |
||||
|
#define TSTH10L (*(unsigned char volatile xdata *)0xfb65) |
||||
|
#define TSTH11 (*(unsigned int volatile xdata *)0xfb66) |
||||
|
#define TSTH11H (*(unsigned char volatile xdata *)0xfb66) |
||||
|
#define TSTH11L (*(unsigned char volatile xdata *)0xfb67) |
||||
|
#define TSTH12 (*(unsigned int volatile xdata *)0xfb68) |
||||
|
#define TSTH12H (*(unsigned char volatile xdata *)0xfb68) |
||||
|
#define TSTH12L (*(unsigned char volatile xdata *)0xfb69) |
||||
|
#define TSTH13 (*(unsigned int volatile xdata *)0xfb6a) |
||||
|
#define TSTH13H (*(unsigned char volatile xdata *)0xfb6a) |
||||
|
#define TSTH13L (*(unsigned char volatile xdata *)0xfb6b) |
||||
|
#define TSTH14 (*(unsigned int volatile xdata *)0xfb6c) |
||||
|
#define TSTH14H (*(unsigned char volatile xdata *)0xfb6c) |
||||
|
#define TSTH14L (*(unsigned char volatile xdata *)0xfb6d) |
||||
|
#define TSTH15 (*(unsigned int volatile xdata *)0xfb6e) |
||||
|
#define TSTH15H (*(unsigned char volatile xdata *)0xfb6e) |
||||
|
#define TSTH15L (*(unsigned char volatile xdata *)0xfb6f) |
||||
|
|
||||
|
/////////////////////////////////////////////////
|
||||
|
//FA00H-FAFFH
|
||||
|
/////////////////////////////////////////////////
|
||||
|
|
||||
|
|
||||
|
/////////////////////////////////////////////////
|
||||
|
|
||||
|
#endif |
||||
|
|
@ -0,0 +1,223 @@ |
|||||
|
////////////////////////////////////////////////////////////////////////////
|
||||
|
///@copyright Copyright (c) 2018, 传控科技 All rights reserved.
|
||||
|
///-------------------------------------------------------------------------
|
||||
|
/// @file msp_eeprom.c
|
||||
|
/// @brief msp @ driver config
|
||||
|
///-------------------------------------------------------------------------
|
||||
|
/// @version 1.0
|
||||
|
/// @author CC
|
||||
|
/// @date 20190106
|
||||
|
/// @note cc_AS_stc02 由stc-isp v6.0860
|
||||
|
//////////////////////////////////////////////////////////////////////////////
|
||||
|
#include "eeprom.h" |
||||
|
#include "../bsp/bsp_config.h" |
||||
|
|
||||
|
struct eeprom_block_t eep_block; |
||||
|
|
||||
|
#if(TYPE_MCU == TYPE_MCU_STC_8A || TYPE_MCU == TYPE_MCU_STC_8F) |
||||
|
#define WT_30M 0x80 |
||||
|
#define WT_24M 0x81 |
||||
|
#define WT_20M 0x82 |
||||
|
#define WT_12M 0x83 |
||||
|
#define WT_6M 0x84 |
||||
|
#define WT_3M 0x85 |
||||
|
#define WT_2M 0x86 |
||||
|
#define WT_1M 0x87 |
||||
|
|
||||
|
|
||||
|
void L0_Iap_Idle() |
||||
|
{ |
||||
|
IAP_CONTR = 0; //关闭IAP功能
|
||||
|
IAP_CMD = 0; //清除命令寄存器
|
||||
|
IAP_TRIG = 0; //清除触发寄存器
|
||||
|
IAP_ADDRH = 0x80; //将地址设置到非IAP区域
|
||||
|
IAP_ADDRL = 0; |
||||
|
} |
||||
|
|
||||
|
char L0_Iap_Read(vU16 addr) |
||||
|
{ |
||||
|
char dat; |
||||
|
|
||||
|
IAP_CONTR = WT_12M; //使能IAP
|
||||
|
IAP_CMD = 1; //设置IAP读命令
|
||||
|
IAP_ADDRL = addr; //设置IAP低地址
|
||||
|
IAP_ADDRH = addr >> 8; //设置IAP高地址
|
||||
|
IAP_TRIG = 0x5a; //写触发命令(0x5a)
|
||||
|
IAP_TRIG = 0xa5; //写触发命令(0xa5)
|
||||
|
_nop_(); |
||||
|
dat = IAP_DATA; //读IAP数据
|
||||
|
L0_Iap_Idle(); //关闭IAP功能
|
||||
|
|
||||
|
return dat; |
||||
|
} |
||||
|
|
||||
|
void L0_Iap_Program(vU16 addr, char dat) |
||||
|
{ |
||||
|
IAP_CONTR = WT_12M; //使能IAP
|
||||
|
IAP_CMD = 2; //设置IAP写命令
|
||||
|
IAP_ADDRL = addr; //设置IAP低地址
|
||||
|
IAP_ADDRH = addr >> 8; //设置IAP高地址
|
||||
|
IAP_DATA = dat; //写IAP数据
|
||||
|
IAP_TRIG = 0x5a; //写触发命令(0x5a)
|
||||
|
IAP_TRIG = 0xa5; //写触发命令(0xa5)
|
||||
|
_nop_(); |
||||
|
L0_Iap_Idle(); //关闭IAP功能
|
||||
|
} |
||||
|
|
||||
|
///每个扇区512字节
|
||||
|
///指定地址可以为当前扇区内的任意地址,都会完整擦除当前扇区
|
||||
|
void L0_Iap_Erase(vU16 addr) |
||||
|
{ |
||||
|
IAP_CONTR = WT_12M; //使能IAP
|
||||
|
IAP_CMD = 3; //设置IAP擦除命令
|
||||
|
IAP_ADDRL = addr; //设置IAP低地址
|
||||
|
IAP_ADDRH = addr >> 8; //设置IAP高地址
|
||||
|
IAP_TRIG = 0x5a; //写触发命令(0x5a)
|
||||
|
IAP_TRIG = 0xa5; //写触发命令(0xa5)
|
||||
|
_nop_(); //
|
||||
|
L0_Iap_Idle(); //关闭IAP功能
|
||||
|
} |
||||
|
|
||||
|
#elif (TYPE_MCU == TYPE_MCU_STC_8G || TYPE_MCU == TYPE_MCU_STC_8H) |
||||
|
void L0_Iap_Idle() |
||||
|
{ |
||||
|
IAP_CONTR = 0; //关闭IAP功能
|
||||
|
IAP_CMD = 0; //清除命令寄存器
|
||||
|
IAP_TRIG = 0; //清除触发寄存器
|
||||
|
IAP_ADDRH = 0x80; //将地址设置到非IAP区域
|
||||
|
IAP_ADDRL = 0; |
||||
|
} |
||||
|
|
||||
|
char L0_Iap_Read(vU16 addr) |
||||
|
{ |
||||
|
char dat; |
||||
|
|
||||
|
IAP_CONTR = 0x80; //使能IAP
|
||||
|
IAP_TPS = 12; |
||||
|
IAP_CMD = 1; //设置IAP读命令
|
||||
|
IAP_ADDRL = addr; //设置IAP低地址
|
||||
|
IAP_ADDRH = addr >> 8; //设置IAP高地址
|
||||
|
IAP_TRIG = 0x5a; //写触发命令(0x5a)
|
||||
|
IAP_TRIG = 0xa5; //写触发命令(0xa5)
|
||||
|
_nop_(); |
||||
|
dat = IAP_DATA; //读IAP数据
|
||||
|
L0_Iap_Idle(); //关闭IAP功能
|
||||
|
|
||||
|
return dat; |
||||
|
} |
||||
|
|
||||
|
void L0_Iap_Program(vU16 addr, char dat) |
||||
|
{ |
||||
|
IAP_CONTR = 0x80; //使能IAP
|
||||
|
IAP_TPS = 12; //设置擦除等待参数 12MHz
|
||||
|
IAP_CMD = 2; //设置IAP写命令
|
||||
|
IAP_ADDRL = addr; //设置IAP低地址
|
||||
|
IAP_ADDRH = addr >> 8; //设置IAP高地址
|
||||
|
IAP_DATA = dat; //写IAP数据
|
||||
|
IAP_TRIG = 0x5a; //写触发命令(0x5a)
|
||||
|
IAP_TRIG = 0xa5; //写触发命令(0xa5)
|
||||
|
_nop_(); |
||||
|
L0_Iap_Idle(); //关闭IAP功能
|
||||
|
} |
||||
|
|
||||
|
///每个扇区512字节
|
||||
|
///指定地址可以为当前扇区内的任意地址,都会完整擦除当前扇区
|
||||
|
void L0_Iap_Erase(vU16 addr) |
||||
|
{ |
||||
|
IAP_CONTR = 0x80; //使能IAP
|
||||
|
IAP_TPS = 12; //设置擦除等待参数 12MHz
|
||||
|
IAP_CMD = 3; //设置IAP擦除命令
|
||||
|
IAP_ADDRL = addr; //设置IAP低地址
|
||||
|
IAP_ADDRH = addr >> 8; //设置IAP高地址
|
||||
|
IAP_TRIG = 0x5a; //写触发命令(0x5a)
|
||||
|
IAP_TRIG = 0xa5; //写触发命令(0xa5)
|
||||
|
_nop_(); //
|
||||
|
L0_Iap_Idle(); //关闭IAP功能
|
||||
|
} |
||||
|
#endif |
||||
|
|
||||
|
|
||||
|
void L0_Iap_Program_array(vU16 addr,U8 *buf,U8 len) |
||||
|
{ |
||||
|
U8 i = 0; |
||||
|
for(i=0;i<len;i++) |
||||
|
{ |
||||
|
L0_Iap_Program(addr + i,buf[i]); |
||||
|
} |
||||
|
} |
||||
|
|
||||
|
void L0_Iap_Read_array(vU16 addr,U8 *buf,U8 len) |
||||
|
{ |
||||
|
U8 i = 0; |
||||
|
for(i=0;i<len;i++) |
||||
|
{ |
||||
|
buf[i] = L0_Iap_Read(addr + i); |
||||
|
} |
||||
|
} |
||||
|
|
||||
|
|
||||
|
//处于节省空间考虑,eeprom读取的数据直接存放到了用户提供的buf中,
|
||||
|
//如果buf长度过小,可能引起内存错误
|
||||
|
U8 L1_eep_read_block(U8 sector, U8 block, U16 blocksize, U8 *buf, U16 *plen) |
||||
|
{ |
||||
|
U16 i,addr = D_EEP_SECTOR_SIZE * sector + blocksize * block; |
||||
|
//读取整块
|
||||
|
L0_Iap_Read_array(addr, (U8*)&eep_block, sizeof(eep_block)); |
||||
|
if(eep_block.filter[0] == D_EEP_BLOCK_FILTER0 && eep_block.filter[1] == D_EEP_BLOCK_FILTER1) |
||||
|
{ |
||||
|
U8 crc[2] = {0,0}; |
||||
|
crc16(crc, eep_block.filter, 2 + 2 + D_EEP_SECTOR_BLOCK_BUF_SIZE); |
||||
|
if(eep_block.crc[0] == crc[0] && eep_block.crc[1] == crc[1]) |
||||
|
{ |
||||
|
U16 len = (U16)eep_block.len[0] << 8 | eep_block.len[1]; |
||||
|
for(i=0;i<len;i++) |
||||
|
{ |
||||
|
buf[i] = eep_block.buf[i]; |
||||
|
} |
||||
|
if(plen != NULL) |
||||
|
{ |
||||
|
*plen = len; |
||||
|
} |
||||
|
L0_uart0_uc('#'); |
||||
|
return 0; //ok
|
||||
|
} |
||||
|
} |
||||
|
return 1; //error
|
||||
|
} |
||||
|
|
||||
|
U8 L1_eep_write_block(U8 sector, U8 block, U16 blocksize, const U8 *buf, U16 len, U8 sectorEraseFlag) |
||||
|
{ |
||||
|
U16 i, addr = D_EEP_SECTOR_SIZE * sector + blocksize * block; |
||||
|
if(len > D_EEP_SECTOR_BLOCK_BUF_SIZE) |
||||
|
{ |
||||
|
//L0_uart0_sendstr("eep write error.");
|
||||
|
return 1; |
||||
|
} |
||||
|
|
||||
|
Lc_memset((U8*)&eep_block,0,sizeof(eep_block)); |
||||
|
eep_block.filter[0] = D_EEP_BLOCK_FILTER0; |
||||
|
eep_block.filter[1] = D_EEP_BLOCK_FILTER1; |
||||
|
eep_block.len[0] = len >> 8 & 0xFF; |
||||
|
eep_block.len[1] = len >> 0 & 0xFF; |
||||
|
for(i=0;i<len;i++) |
||||
|
{ |
||||
|
eep_block.buf[i] = buf[i]; |
||||
|
} |
||||
|
crc16(eep_block.crc, eep_block.filter, 2 + 2 + D_EEP_SECTOR_BLOCK_BUF_SIZE); |
||||
|
if(sectorEraseFlag == 1) |
||||
|
{ |
||||
|
L0_Iap_Erase(addr); |
||||
|
} |
||||
|
//写入整块
|
||||
|
L0_Iap_Program_array(addr, (U8*)&eep_block, sizeof(eep_block)); |
||||
|
return 0; |
||||
|
} |
||||
|
|
||||
|
U8 L1_eep_erase_sector(U8 sector) |
||||
|
{ |
||||
|
U16 addr = D_EEP_SECTOR_SIZE * sector; |
||||
|
L0_Iap_Erase(addr); |
||||
|
return 0; |
||||
|
} |
||||
|
|
||||
|
|
@ -0,0 +1,56 @@ |
|||||
|
//////////////////////////////////////////////////////////////////////////
|
||||
|
/// COPYRIGHT NOTICE
|
||||
|
/// Copyright (c) 2018, 传控科技
|
||||
|
/// All rights reserved.
|
||||
|
///
|
||||
|
/// @file msp_eeprom
|
||||
|
/// @brief msp_eeprom
|
||||
|
/// @info
|
||||
|
///(本文件实现的功能的详述)
|
||||
|
///
|
||||
|
/// @version 1.1 CCsens technology
|
||||
|
/// @author CC
|
||||
|
/// @date 20190106
|
||||
|
|
||||
|
//
|
||||
|
//////////////////////////////////////////////////////////////////////////
|
||||
|
|
||||
|
#ifndef _msp_eeprom_H_ |
||||
|
#define _msp_eeprom_H_ |
||||
|
|
||||
|
#include "../clib/type.h" |
||||
|
#include "../clib/clib.h" |
||||
|
#include "../ctask/tick.h" |
||||
|
#include "uart0.h" |
||||
|
|
||||
|
/**
|
||||
|
* EEPROM 存储结构 |
||||
|
* filter0 + filter1 + len0 + len1 + {data} + crc0 + crc1 |
||||
|
*/ |
||||
|
#define D_EEP_SECTOR_BLOCK_BUF_SIZE (D_EEP_SECTOR_BLOCK_SIZE - 6) |
||||
|
typedef struct eeprom_block_t |
||||
|
{ |
||||
|
U8 filter[2]; //filter
|
||||
|
U8 len[2]; //有效数据的个数
|
||||
|
U8 buf[D_EEP_SECTOR_BLOCK_BUF_SIZE]; |
||||
|
U8 crc[2]; //从filter开始进行整体校验
|
||||
|
}EEPROM_BLOCK; |
||||
|
|
||||
|
extern struct eeprom_block_t eep_block; |
||||
|
extern U8 L1_eep_read_block(U8 sector, U8 block, U16 blocksize, U8 *buf, U16 *plen); |
||||
|
extern U8 L1_eep_write_block(U8 sector, U8 block, U16 blocksize, const U8 *buf, U16 len, U8 sectorEraseFlag); |
||||
|
extern U8 L1_eep_erase_sector(U8 sector); |
||||
|
|
||||
|
|
||||
|
///每个扇区512字节
|
||||
|
extern void L0_Iap_Erase(vU16 addr); |
||||
|
extern void L0_Iap_Program(vU16 addr, char dat); |
||||
|
extern char L0_Iap_Read(vU16 addr); |
||||
|
extern void L0_Iap_Program_array(vU16 addr,U8 *buf,U8 len); |
||||
|
extern void L0_Iap_Read_array(vU16 addr,U8 *buf,U8 len); |
||||
|
extern void L1_Iap_main(void); |
||||
|
extern void L3_eeprom_fun(U8 *pPara); |
||||
|
|
||||
|
#endif// #ifndef _msp_eeprom_H_
|
||||
|
|
||||
|
|
@ -1,170 +0,0 @@ |
|||||
////////////////////////////////////////////////////////////////////////////
|
|
||||
///@copyright Copyright (c) 2018, 传控科技 All rights reserved.
|
|
||||
///-------------------------------------------------------------------------
|
|
||||
/// @file msp_eeprom.c
|
|
||||
/// @brief msp @ driver config
|
|
||||
///-------------------------------------------------------------------------
|
|
||||
/// @version 1.0
|
|
||||
/// @author CC
|
|
||||
/// @date 20190106
|
|
||||
/// @note cc_AS_stc02 由stc-isp v6.0860
|
|
||||
//////////////////////////////////////////////////////////////////////////////
|
|
||||
#include "msp_eeprom.h" |
|
||||
|
|
||||
#include "../tpc/tpc_uart.h" |
|
||||
|
|
||||
|
|
||||
#define WT_30M 0x80 |
|
||||
#define WT_24M 0x81 |
|
||||
#define WT_20M 0x82 |
|
||||
#define WT_12M 0x83 |
|
||||
#define WT_6M 0x84 |
|
||||
#define WT_3M 0x85 |
|
||||
#define WT_2M 0x86 |
|
||||
#define WT_1M 0x87 |
|
||||
|
|
||||
|
|
||||
U_F16 uf_ee_add; |
|
||||
|
|
||||
|
|
||||
void L0_Iap_Idle() |
|
||||
{ |
|
||||
IAP_CONTR = 0; //关闭IAP功能
|
|
||||
IAP_CMD = 0; //清除命令寄存器
|
|
||||
IAP_TRIG = 0; //清除触发寄存器
|
|
||||
IAP_ADDRH = 0x80; //将地址设置到非IAP区域
|
|
||||
IAP_ADDRL = 0; |
|
||||
} |
|
||||
|
|
||||
char L0_Iap_Read(vU16 addr) |
|
||||
{ |
|
||||
char dat; |
|
||||
|
|
||||
IAP_CONTR = WT_12M; //使能IAP
|
|
||||
IAP_CMD = 1; //设置IAP读命令
|
|
||||
IAP_ADDRL = addr; //设置IAP低地址
|
|
||||
IAP_ADDRH = addr >> 8; //设置IAP高地址
|
|
||||
IAP_TRIG = 0x5a; //写触发命令(0x5a)
|
|
||||
IAP_TRIG = 0xa5; //写触发命令(0xa5)
|
|
||||
_nop_(); |
|
||||
dat = IAP_DATA; //读IAP数据
|
|
||||
L0_Iap_Idle(); //关闭IAP功能
|
|
||||
|
|
||||
return dat; |
|
||||
} |
|
||||
|
|
||||
void L0_Iap_Program(vU16 addr, char dat) |
|
||||
{ |
|
||||
IAP_CONTR = WT_12M; //使能IAP
|
|
||||
IAP_CMD = 2; //设置IAP写命令
|
|
||||
IAP_ADDRL = addr; //设置IAP低地址
|
|
||||
IAP_ADDRH = addr >> 8; //设置IAP高地址
|
|
||||
IAP_DATA = dat; //写IAP数据
|
|
||||
IAP_TRIG = 0x5a; //写触发命令(0x5a)
|
|
||||
IAP_TRIG = 0xa5; //写触发命令(0xa5)
|
|
||||
_nop_(); |
|
||||
L0_Iap_Idle(); //关闭IAP功能
|
|
||||
} |
|
||||
|
|
||||
///每个扇区512字节
|
|
||||
///指定地址可以为当前扇区内的任意地址,都会完整擦除当前扇区
|
|
||||
void L0_Iap_Erase(vU16 addr) |
|
||||
{ |
|
||||
IAP_CONTR = WT_12M; //使能IAP
|
|
||||
IAP_CMD = 3; //设置IAP擦除命令
|
|
||||
IAP_ADDRL = addr; //设置IAP低地址
|
|
||||
IAP_ADDRH = addr >> 8; //设置IAP高地址
|
|
||||
IAP_TRIG = 0x5a; //写触发命令(0x5a)
|
|
||||
IAP_TRIG = 0xa5; //写触发命令(0xa5)
|
|
||||
_nop_(); //
|
|
||||
L0_Iap_Idle(); //关闭IAP功能
|
|
||||
} |
|
||||
|
|
||||
void L0_Iap_Program_array(vU16 addr,U8 *buf,U8 len) |
|
||||
{ |
|
||||
U8 i = 0; |
|
||||
for(i=0;i<len;i++) |
|
||||
{ |
|
||||
L0_Iap_Program(addr + i,buf[i]); |
|
||||
} |
|
||||
} |
|
||||
|
|
||||
void L0_Iap_Read_array(vU16 addr,U8 *buf,U8 len) |
|
||||
{ |
|
||||
U8 i = 0; |
|
||||
for(i=0;i<len;i++) |
|
||||
{ |
|
||||
buf[i] = L0_Iap_Read(addr + i); |
|
||||
} |
|
||||
} |
|
||||
|
|
||||
void L1_Iap_main(void) |
|
||||
{ |
|
||||
int i; |
|
||||
U16 addr = 0x00; |
|
||||
U8 buf[30]; |
|
||||
L0_Iap_Read_array(addr,buf,30); |
|
||||
L0_uart0_uc('^');Lc_delay_ms(2); |
|
||||
for(i=0;i<30;i++) |
|
||||
{ |
|
||||
L0_uart0_uchex(buf[i]); |
|
||||
Lc_delay_ms(2); |
|
||||
} |
|
||||
L0_uart0_uc('$'); |
|
||||
} |
|
||||
|
|
||||
#if 0 |
|
||||
void L1_Iap_main(void) |
|
||||
{ |
|
||||
int i; |
|
||||
U16 addr = 0x00; |
|
||||
U8 buf[10]; |
|
||||
|
|
||||
L0_Iap_Erase(addr); |
|
||||
L0_Iap_Program_array(addr,"abcdefg",7); |
|
||||
L0_Iap_Read_array(addr,buf,10); |
|
||||
|
|
||||
for(i=0;i<10;i++) |
|
||||
{ |
|
||||
Lc_delay_ms(2); |
|
||||
L0_uart0_uc(buf[i]); |
|
||||
} |
|
||||
|
|
||||
L0_Iap_Erase(addr + 0x200); |
|
||||
L0_Iap_Program_array(addr + 0x200,"ABCDEFG",7); |
|
||||
L0_Iap_Read_array(addr + 0x200,buf,10); |
|
||||
|
|
||||
for(i=0;i<10;i++) |
|
||||
{ |
|
||||
Lc_delay_ms(2); |
|
||||
L0_uart0_uc(buf[i]); |
|
||||
} |
|
||||
|
|
||||
#if 0 |
|
||||
for(i=0; i<0x1000; i++) |
|
||||
{ |
|
||||
L0_Iap_Program(i,0); |
|
||||
} |
|
||||
|
|
||||
for(i = 0;i < 0x1010; i++) |
|
||||
{ |
|
||||
//L0_uart0_uchex(i%256);
|
|
||||
L0_uart0_uchex(L0_Iap_Read(addr + i)); |
|
||||
|
|
||||
if(i==0x1000-1) |
|
||||
{ |
|
||||
Lc_delay_ms(100); |
|
||||
L0_uart0_uchex(i>>8 & 0xFF); |
|
||||
L0_uart0_uchex(i>>0 & 0xFF); |
|
||||
} |
|
||||
} |
|
||||
#endif |
|
||||
Lc_delay_ms(100); |
|
||||
L0_uart0_uc('%'); |
|
||||
|
|
||||
while(1); |
|
||||
} |
|
||||
#endif |
|
||||
|
|
||||
|
|
||||
|
|
Loading…
Reference in new issue